Method for making a heterojunction bipolar transistor with improved high frequency response

Claim 2

A process for making a heterojunction bipolar transistor comprising the steps of: depositing a patterned subcollector layer of a first type of semiconductor material on a semi-insulating substrate of a second type of semiconductor material; depositing an insulating layer over said patterned subcollector layer and said semi-insulating substrate in the region surrounding said patterned subcollector layer; forming a hole through said insulating layer to said subcollector layer defining a collector region; epitaxially growing a first layer of said second type of semiconductor material on said subcollector layer in said hole to form a collector; epitaxially growing a first layer of said first type of semiconductor material on said collector to form a base, the periphery of said base being cantilevered over said insulating layer; epitaxially growing at least a second layer of said second semiconducting material on said base; epitaxially growing a second layer of said first type of semiconducting material on said at least a second layer to form an emitter; etching said emitter and said at least a second layer to form an emitter mesa concentric with said hole formed in said insulating layer, said emitter mesa having a shape and a size substantially equal to the shape and size of said hole; and providing metallic electrodes electrically contacting said emitter, said base and said patterned subcollector layer.

Claim 3

The process of claim 1 wherein said step of depositing a patterned layer comprises the steps of: depositing said first type of semiconductor material on said substrate to form a layer of said first type of semiconductor material; and patterning said layer of said first type of semiconductor material using a photolithography process to form said patterned semiconductor layer.

Claim 4

The process of claim 1 wherein said step of epitaxially growing said first layer of said second type of semiconducting material comprises the steps of: epitaxially growing a first n + type layer of said second type of semiconducting material on said patterned subcollector on said patterned subcollector layer in said hole; and epitaxially growing a first n-type layer of said second type of semiconductor material on said first n + type layer to form said collector.

Claim 5

The process of claim 3 wherein said step of epitaxially growing at least a second layer of said second type of semiconductor material comprises the steps of: epitaxially growing a second n-type layer of said second type semiconducting material on said base; and epitaxially growing a second n + layer of said second type of semiconductor material on said second n-type layer.

Claim 6

The process of claim 4 wherein said step of etching comprises: forming a mask on said emitter concentric with said hole using photolithography techniques; ion bombarding to ion etch said emitter, said second n + semiconductor layer of said second type and said n semiconducting layer of said second type in the region circumscribing said mask to form said emitter mesa.

Claim 7

The process of claim 1 wherein said emitter mesa has a vertical surface circumscribing said emitter mesa, said process further includes the step of depositing and insulating layer covering said vertical surface.

Claim 8

The process of claim 1 wherein said step of providing metallic electrodes comprises the step of depositing said metallic electrodes on said base using said emitter mesa as a self-aligned mask.

Claim 9

The process of claim 1 wherein said step of providing metallic electrodes comprises the steps of forming holes through said insulating layer to said subcollector layer and depositing said metallic electrodes through said holes.

Claim 10

The process of claim 1 wherein said steps of epitaxially growing said first and second layers of said first type of semiconducting surfaces comprises the step of epitaxially growing said first and second layers of said first type of semiconductor material using organometallic vapor phase epitaxy.

Claim 11

The process of claim 1 wherein said steps of epitaxially growing said first and second layers of said second type of semiconducting material comprises the steps of epitaxially growing said first and second layers of said type of semiconductor material using organometallic vapor phase epitaxy.

Claim 12

The process of claim 1 wherein said first type of semiconducting material is indium phosphide and said second type of semiconductor material is indium gallium arsenide.

Claim 13

A process of making a heterojunction bipolar transistor comprising the steps of: forming a patterned subcollector layer of a first type of semiconducting material on a semi-insulating substrate of a second type of semiconducting material; depositing a layer of insulating material on said subcollector layer; etching a first hole through said insulating material to expose a portion of said subcollector layer therethrough; placing said substrate with said subcollector layer and said insulating layer in an organometallic vapor phase epitaxy system; epitaxially growing in said organometallic vapor phase epitaxy system a first n + layer of said second type of semiconductor material on said subcollector layer within said hole; epitaxially growing a first n-type layer of said second type of semiconductor material on said first n + layer of said second type of semiconducting material within said hole to form a collector; epitaxially growing a p + type layer of said first type of semiconducting material on said collector to form a base, the peripheral region of said base extending over a portion of said layer insulating material circumscribing said hole; epitaxially growing a second n-type layer of said second type of semiconductor material on said base; epitaxially growing a second n + type layer of said second type of semiconducting layer on said second n-type layer of said second type of semiconducting material; epitaxially growing a second n + layer of said first type of semiconducting material on said second n-type layer of said second type of semiconducting material to form an emitter; forming a mask on the surface of said emitter vertically aligned with said hole, said mask having a shape and size substantially identical to the shape and size of said hole; etching said n + layer of said first type of semiconducting material and said second n + and n-type layers of said second type of semiconducting material to form an emitter mesa centrally disposed on said base, said etching exposing a lateral portion of said base circumscribing said emitter mesa; depositing a second layer of insulating covering the side walls of said emitter mesa; depositing a base metallic electrode on said exposed lateral portion of said base using said emitter mesa as a self-aligned mask; depositing an emitter metallic electrode on said emitter; etching at least a second hole through said first insulating material offset from said first hole to expose a portion of said subcollector layer; and depositing a collector metallic electrode on said subcollector layer through said second hole.

Claim 14

A process of making a heterojunction bipolar transistor comprising the steps of: forming a patterned subcollector layer of a first type of semiconducting material on a semi-insulating substrate of a second type of semiconducting material; depositing a layer of insulating material on said subcollector layer; etching a first hole through said insulating material to expose a portion of said subcollector layer therethrough; placing said substrate with said subcollector layer and said insulating layer in an organometallic vapor phase epitaxy system; epitaxially growing in said organometallic vapor phase epitaxy system a first n + layer of said second type of semiconductor material on said subcollector layer within said hole; epitaxially growing a first n-type layer of said second type of semiconductor material on said first n + layer of said second type of semiconducting material within said hole to form a collector; epitaxially growing a p + type layer of said first type of semiconducting material on said collector to form a base, the peripheral region of said base extending over a portion of said layer insulating material circumscribing said hole; epitaxially growing a second n-type layer of said second type of semiconductor material on said base; epitaxially growing a second n + type layer of said second type of semiconducting layer on said second n-type layer of said second type of semiconducting material; epitaxially growing a second n + layer of said first type of semiconducting material on said second n-type layer of said second type of semiconducting material to form an emitter; forming a mask on the surface of said emitter vertically aligned with said hole, said mask having a shape and size substantially identical to the shape and size of said hole; etching said n + layer of said first type of semiconducting material and said second n + and n-type layers of said second type of semiconducting material to form an emitter mesa centrally disposed on said base, said etching exposing a lateral portion of said base circumscribing said emitter mesa; depositing a second layer of insulating covering the side walls of said emitter mesa; depositing a base metallic electrode on said exposed lateral portion of said base using said emitter mesa as a self-aligned mask; depositing an emitter metallic electrode on said emitter; etching at least a second hole through said first insulating material offset from said first hole to expose a portion of said subcollector layer; and depositing a collector metallic electrode on said subcollector layer through said second hole.

Claim 15

The process of claim 12 wherein said first type of semiconducting material is indium gallium arsenide (InGaAs) and said second type of semiconducting material is indium phosphide (InP).

Claim 16

The process of claim 12 wherein said first type of semiconducting material is indium gallium arsenic phosphide (InGaAsP) and said second type of semiconducting material is indium phosphide (InP).

Claim 17

The process of claim 12 wherein said first type of semiconducting material is indium gallium arsenide (InGaAs) and said second type of semiconducting material is aluminum indium arsenide (AlInAs).

Claim 18

The process of claim 12 wherein said first type of semiconducting material is gallium arsenide (GaAs) and said second type of semiconducting material is aluminum gallium arsenide (AlGaAs).

Claim 19

The process of claim 12 wherein said first type of semiconducting material is germanium (Ge) and said second type of semiconducting material is germanium silicon (GeSi).