US4914049A
Expired / Lapsed
US
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Method of fabricating a heterojunction bipolar transistor
Assignee: NXP USA Inc
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Filing: 1989-10-16
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Granted: 1990-04-03
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Expires: 2009-10-16
Abstract
Abstract A heterojunction bipolar transistor having a planar surface topology, reduced lateral dimensions and a base electrode aligned to both the emitter and collector electrodes is fabricated by forming sub-collector, collector, base and one or more emitter layers on a substrate. An opening extending to the sub-collector layer is then formed and a first portion of the collector electrode is formed therein so that the sidewalls of the opening are not contacted by the first portion. Dielectric material is then formed between the sidewalls of the opening and the first portion of the collector electrode. A second portion of the collector electrode is then formed on the first portion of the collector electrode along with an emitter electrode so that the second portion of the collector electrode and the emitter electrode are substantially planar. After then exposing the base layer, the self-aligned base electrode is formed between the second portion of the collector electrode and the emitter electrode.
Inventors
- 👤 Jenn-Hwa Huang
- 👤 Luke Mang
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 05:11
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/34; H10D10/00; H10D10/01; H10D10/021; H10D64/00; H10D64/01; H10D64/011; H10D62/00; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/011; Y10S148/072
Claims Analysis
Total Claims: 17
Claim 1
Independent Claim
154 words
A method of fabricating a heterojunction bipolar transistor comprising the steps of: providing a substrate; forming one or more collector layers on said substrate; forming a base layer on said one or more collector layers; forming one or more emitter layers on said base layer; forming an opening extending through said one or more emitter layers and said base layer, said opening extending to said one or more collector layers; forming a first collector metal in said opening so that said first collector metal is not in contact with any sidewalls of said opening; forming dielectric material in said opening between said first collector metal and said sidewalls of said opening; forming emitter metal on said one or more emitter layers and a second collector metal on said first collector metal, said emitter metal and said second collector metal being substantially planar; exposing said base layer; and forming base metal on said base layer.
Claim 2
Independent Claim
154 words
A method of fabricating a heterojunction bipolar transistor comprising the steps of: providing a substrate; forming one or more collector layers on said substrate; forming a base layer on said one or more collector layers; forming one or more emitter layers on said base layer; forming an opening extending through said one or more emitter layers and said base layer, said opening extending to said one or more collector layers; forming a first collector metal in said opening so that said first collector metal is not in contact with any sidewalls of said opening; forming dielectric material in said opening between said first collector metal and said sidewalls of said opening; forming emitter metal on said one or more emitter layers and a second collector metal on said first collector metal, said emitter metal and said second collector metal being substantially planar; exposing said base layer; and forming base metal on said base layer.
Claim 3
Dependent Claim
68 words
The method of claim 1 where the substrate comprises semi-insulating gallium arsenide, the one or more collector layers comprise a sub-collector layer and a collector layer both being comprised of gallium arsenide, the base layer comprises gallium arsenide and the one or more emitter layers comprise an aluminum gallium arsenide layer disposed on said base layer and a gallium arsenide layer disposed on said aluminum gallium arsenide layer.
Claim 4
Dependent Claim
46 words
The method of claim 1 wherein the forming an opening step includes forming a photoresist layer on the one or more emitter layers, forming a mask from said photoresist layer and using said mask to etch an opening extending to the one or more collector layers.
Claim 5
Dependent Claim
19 words
The method of claim 3 wherein the photoresist mask is lifted-off following the forming a first collector metal step.
Claim 6
Dependent Claim
57 words
The method of claim 1 wherein the forming dielectric material step comprises the steps of: forming a dielectric layer in the opening and on the structure; forming a photoresist layer on the dielectric layer; and etching said photoresist layer and said dielectric layer to the one or more emitter layers so that the structure is substantially planar.
Claim 7
Dependent Claim
30 words
The method of claim 1 wherein the exposing said base layer step includes removing the one or more emitter layers from the structure excepting that disposed beneath the emitter metal.
Claim 8
Dependent Claim
40 words
The method of claim 6 wherein the forming base metal step includes forming base metal between the emitter metal and the second collector metal so that said base metal is self-aligned to said emitter metal and said second collector metal.
Claim 9
Independent Claim
256 words
A method of fabricating a heterojunction bipolar transistor comprising the steps of: providing a semi-insulating gallium arsenide substrate; forming a gallium arsenide sub-collector layer on said substrate; forming a gallium arsenide collector layer on said sub-collector layer; forming a gallium arsenide base layer on said collector layer; forming an aluminum gallium arsenide emitter layer on said base layer; forming a gallium arsenide emitter cap layer on said first emitter layer; forming a first photoresist mask on said second emitter layer; forming an opening using said first photoresist mask, said opening extending to said sub-collector layer; forming a first collector metal in said opening so that said first collector metal is not in contact with the sidewalls of said opening; removing said first photoresist mask; forming a dielectric layer on the structure including in said opening between said sidewalls of said opening and said first collector metal; forming a photoresist layer on said dielectric layer and etching through said photoresist layer and said dielectric layer to said emitter cap layer so that the structure is substantially planar; forming a second photoresist mask and using said second mask to form emitter metal on said second emitter layer and second collector metal on said first collector metal; removing said second photoresist mask; removing said emitter layer and said emitter cap layer excepting the portions disposed beneath said emitter metal to expose said base layer; and forming base metal on said base layer between said emitter metal and said second collector metal so that said base metal formation is self-aligned.
Claim 10
Independent Claim
256 words
A method of fabricating a heterojunction bipolar transistor comprising the steps of: providing a semi-insulating gallium arsenide substrate; forming a gallium arsenide sub-collector layer on said substrate; forming a gallium arsenide collector layer on said sub-collector layer; forming a gallium arsenide base layer on said collector layer; forming an aluminum gallium arsenide emitter layer on said base layer; forming a gallium arsenide emitter cap layer on said first emitter layer; forming a first photoresist mask on said second emitter layer; forming an opening using said first photoresist mask, said opening extending to said sub-collector layer; forming a first collector metal in said opening so that said first collector metal is not in contact with the sidewalls of said opening; removing said first photoresist mask; forming a dielectric layer on the structure including in said opening between said sidewalls of said opening and said first collector metal; forming a photoresist layer on said dielectric layer and etching through said photoresist layer and said dielectric layer to said emitter cap layer so that the structure is substantially planar; forming a second photoresist mask and using said second mask to form emitter metal on said second emitter layer and second collector metal on said first collector metal; removing said second photoresist mask; removing said emitter layer and said emitter cap layer excepting the portions disposed beneath said emitter metal to expose said base layer; and forming base metal on said base layer between said emitter metal and said second collector metal so that said base metal formation is self-aligned.
Claim 11
Dependent Claim
36 words
The method of claim 8 wherein the first collector metal comprises: a layer of gold-germanium alloy; a layer of nickel formed on said layer of gold-germanium alloy; and a gold layer formed on said nickel layer.
Claim 12
Dependent Claim
25 words
The method of claim 9 wherein the emitter metal and the second collector metal are comprised of the same metals as the first collector metal.
Claim 13
Dependent Claim
33 words
The method of claim 10 wherein the base metal comprises: a layer of titanium; a layer of platinum formed on said titanium layer; and a layer of gold formed on said platinum layer.
Claim 14
Dependent Claim
12 words
The method of claim 9 wherein the dielectric layer comprises silicon dioxide.
Claim 15
Independent Claim
110 words
A method of fabricating a heterojunction bipolar transistor having planar emitter and collector electrodes comprising the steps of: forming an opening extending to a collector layer of the transistor structure; forming a first portion of a collector electrode in said opening; isolating said first portion with a dielectric; forming a second portion of a collector electrode on said first portion; forming an emitter electrode adjacent to and substantially planar with said second portion; exposing a base layer of the transistor structure between said second portion and said emitter electrode; and forming a base electrode on the exposed portion of said base layer between said second portion and said emitter electrode.
Claim 16
Independent Claim
110 words
A method of fabricating a heterojunction bipolar transistor having planar emitter and collector electrodes comprising the steps of: forming an opening extending to a collector layer of the transistor structure; forming a first portion of a collector electrode in said opening; isolating said first portion with a dielectric; forming a second portion of a collector electrode on said first portion; forming an emitter electrode adjacent to and substantially planar with said second portion; exposing a base layer of the transistor structure between said second portion and said emitter electrode; and forming a base electrode on the exposed portion of said base layer between said second portion and said emitter electrode.
Claim 17
Dependent Claim
21 words
The method of claim 13 wherein the forming a second portion and the forming an emitter electrode steps are performed simultaneously.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-04-02 | 1993-10-02 | 1994-04-03 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-04-02 | 1997-10-02 | 1998-04-03 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-04-02 | 2001-10-02 | 2002-04-03 | $7700.00 | Window Closed / Lapsed |