US4789643A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Method of manufacturing a heterojunction bipolar transistor involving etch and refill
Assignee: Mitsubishi Electric Corp
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Filing: 1987-09-16
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Granted: 1988-12-06
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Expires: 2007-09-16
Abstract
Abstract A heterojunction bipolar transistor and method of manufacturing the same is disclosed in which, a semi-insulation layer and an external base layer sequentially epitaxially grown on a collector layer are selectively mesa-etched through a mask of an insulation film provided with an opening so that the external base layer, the semi-insulation layer and the collector layer are selectively exposed. Subsequently an internal base layer and an emitter layer are selectively epitaxially grown in sequence on the exposed regions of the external base layer, the semi-insulation layer and the collector layer. An emitter electrode is formed in a self-aligned manner through the opening of the insulation film. Thus, transistor performance is improved and element size accuracy is improved.
Inventors
- 👤 Yasutomo Kajikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 16:32
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D62/00; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S148/00; Y10S148/011; Y10S148/026; Y10S148/05
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
141 words
A method of manufacturing a heterojunction bipolar transistor, said method comprising: a first step of sequentially epitaxially growing a first conductivity type collector layer, a semi-insulating layer and a second conductivity type external base layer on the upper part of a semi-insulating substrate; a second step of performing selective mesa etching from said external base layer to said collector layer by utilizing a insulation film having a selectively formed opening as a mask to form a cavity exposing said external base layer, said semi-insulating layer and said collector layer; a third step of sequentially epitaxially growing a second conductivity type internal base layer and a first conductivity type emitter layer in said cavity by utilizing said insulation film as a mask; and a fourth step of forming an emitter electrode in a self-aligned manner through said opening of said insulation film.
Claim 2
Independent Claim
141 words
A method of manufacturing a heterojunction bipolar transistor, said method comprising: a first step of sequentially epitaxially growing a first conductivity type collector layer, a semi-insulating layer and a second conductivity type external base layer on the upper part of a semi-insulating substrate; a second step of performing selective mesa etching from said external base layer to said collector layer by utilizing a insulation film having a selectively formed opening as a mask to form a cavity exposing said external base layer, said semi-insulating layer and said collector layer; a third step of sequentially epitaxially growing a second conductivity type internal base layer and a first conductivity type emitter layer in said cavity by utilizing said insulation film as a mask; and a fourth step of forming an emitter electrode in a self-aligned manner through said opening of said insulation film.
Claim 3
Dependent Claim
34 words
A method of manufacturing a heterojunction bipolar transistor in accordance with claim 1, further including a step of epitaxially growing a first conductivity type subcollector layer between said semi-insulating substrate and said collector layer.
Claim 4
Dependent Claim
30 words
A method of manufacturing a heterojunction bipolar transistor in accordance with claim 1, further including a step of epitaxially growing a first conductivity type cap layer on said emitter layer.
Claim 5
Dependent Claim
46 words
A method of manufacturing a heterojunction bipolar transistor in accordance with claim 1, further including a step of forming a base electrode and providing a through hole in said insulation film to form a base electrode connection to said external base layer via said through hole.
Claim 6
Dependent Claim
47 words
A method of manufacturing a heterojunction bipolar transistor in accordance with claim 2, further including a step of forming an electrode cavity from said insulation film to said subcollector layer to form a collector electrode on an exposed region of said subcollector layer in said electrode cavity.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-12-06 | 1992-06-06 | 1992-12-06 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-12-06 | 1996-06-06 | 1996-12-06 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-12-06 | 2000-06-06 | 2000-12-06 | $7700.00 | Window Closed / Lapsed |