US4731340A
Expired / Lapsed
US
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Dual lift-off self aligning process for making heterojunction bipolar transistors
Assignee: Teledyne Scientific and Imaging LLC
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Filing: 1987-02-24
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Granted: 1988-03-15
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Expires: 2007-02-24
Abstract
Abstract A dual lift-off technique is used to provide self-alignment of the emitter area, the emitter contact, and the base contact of a heterojunction, bipolar transistor. A photoresist pattern which defines an emitter adjacent a base contact is formed on a suitable heterojunction bipolar semiconductor wafer. A base contact is formed by etching through the first semiconductor to the heterojunction and depositing metal on the second semiconductor. Dielectric is then deposited on the base contact. The photoresist is then lifted off with its dual covering of dielectric and metal. The emitter contact metal can then be deposited without requiring critical alignment because the base contact is covered with dielectric.
Inventors
- 👤 Mau-Chung F. Chang
- 👤 Peter M. Asbeck
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 09:29
CPC Classifications
H; H10; H10D; H10D10/00; H10D10/01; H10D10/021; H10D10/80; H10D10/821; H10D62/00; H10D62/10; H10D62/113; H10D62/115; H10D62/13; H10D62/137; H10P; H10P76/00; H10P76/20; H10P76/202; H10D62/80; H10D62/85; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/951
Claims Analysis
Total Claims: 22
Claim 1
Independent Claim
190 words
A method of fabricating a heterojunction bipolar transistor (HBT), comprising: providing a heterojunction bipolar semiconductor wafer having a first layer of a semiconductor of one conductivity type, a second layer of a semiconductor of an opposite conductivity type on the first layer forming a first p-n junction, and a third layer of a semiconductor of the one conductivity type on the second layer forming a second p-n junction, at least one of the p-n junctions being a heterojunction; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the third layer through the opening to the second layer; depositing base contact metal on the second layer through the opening; depositing dielectric on the base contact metal and on the sidewalls of the opening; lifting off the photoresist with its overlying dielectric and metal while maintaining dielectric on the sidewalls; defining a location for emitter contact metal of the HBT on the third layer; depositing emitter contact metal on the emitter contact location; providing an opening to the first layer, and; depositing collector contact metal on the first layer through the opening.
Claim 2
Independent Claim
190 words
A method of fabricating a heterojunction bipolar transistor (HBT), comprising: providing a heterojunction bipolar semiconductor wafer having a first layer of a semiconductor of one conductivity type, a second layer of a semiconductor of an opposite conductivity type on the first layer forming a first p-n junction, and a third layer of a semiconductor of the one conductivity type on the second layer forming a second p-n junction, at least one of the p-n junctions being a heterojunction; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the third layer through the opening to the second layer; depositing base contact metal on the second layer through the opening; depositing dielectric on the base contact metal and on the sidewalls of the opening; lifting off the photoresist with its overlying dielectric and metal while maintaining dielectric on the sidewalls; defining a location for emitter contact metal of the HBT on the third layer; depositing emitter contact metal on the emitter contact location; providing an opening to the first layer, and; depositing collector contact metal on the first layer through the opening.
Claim 3
Dependent Claim
26 words
The method as claimed in claim 1 wherein the heterojunction bipolar semiconductor is a single heterojunction bipolar semiconductor and the heterojunction is the first p-n junction.
Claim 4
Dependent Claim
26 words
The method as claimed in claim 1, wherein the heterojunction bipolar semiconductor is a single heterojunction bipolar semiconductor and the heterojunction is the second p-n junction.
Claim 5
Dependent Claim
29 words
The method as claimed in claim 1 wherein the heterojunction bipolar semiconductor is a double heterojunction bipolar semiconductor and the heterojunction is the first and the second p-n junctions.
Claim 6
Dependent Claim
18 words
The method as claimed in claim 1 wherein the wafer includes a cap layer on the third layer.
Claim 7
Dependent Claim
23 words
The method as claimed in claim 5 including the step of etching the cap layer to provide a mesa cap for the HBT.
Claim 8
Dependent Claim
24 words
The method as claimed in claim 1 including the step of isolating an area on the wafer for the HBT by an isolation implant.
Claim 9
Dependent Claim
28 words
The method as claimed in claim 1 including the step of implanting protons into the first layer under the base location prior to depositing the base contact metal.
Claim 10
Dependent Claim
15 words
The method as claimed in claim 1 wherein the semiconductor is a III-V compound semiconductor.
Claim 11
Dependent Claim
22 words
The method as claimed in claim 1 including the step of etching back some of the photoresist prior to depositing the dielectric.
Claim 12
Dependent Claim
200 words
A self-aligned process for making a single heterojunction bipolar transistor (HBT) comprising: providing a heterojunction bipolar semiconductor wafer having a negative conductivity type layer of GaAs, a positive conductivity type layer of GaAs on the negative conductivity type layer of GaAs, and a negative conductivity type layer of AlGaAs on the positive conductivity type layer of GaAs; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the negative conductivity type layer of AlGaAs through the opening down to the positive conductivity type layer of GaAs; implanting protons through the opening into the negative conductivity type layer of GaAs; depositing base contact metal on the GaAs through the opening; depositing dielectric on the base contact metal and on the sidewalls of the opening; lifting off the photoresist with its overlying dielectric and metal while maintaining dielectric on the sidewalls; masking the remaining dielectric and the negative conductivity type layer of AlGaAs except for an emitter location; depositing emitter contact metal on the AlGaAs at the emitter location; providing an opening to the negative conductivity type layer of gaAs; and depositing collector contact metal on the negative conductivity type layer of GaAs.
Claim 13
Dependent Claim
200 words
A self-aligned process for making a single heterojunction bipolar transistor (HBT) comprising: providing a heterojunction bipolar semiconductor wafer having a negative conductivity type layer of GaAs, a positive conductivity type layer of GaAs on the negative conductivity type layer of GaAs, and a negative conductivity type layer of AlGaAs on the positive conductivity type layer of GaAs; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the negative conductivity type layer of AlGaAs through the opening down to the positive conductivity type layer of GaAs; implanting protons through the opening into the negative conductivity type layer of GaAs; depositing base contact metal on the GaAs through the opening; depositing dielectric on the base contact metal and on the sidewalls of the opening; lifting off the photoresist with its overlying dielectric and metal while maintaining dielectric on the sidewalls; masking the remaining dielectric and the negative conductivity type layer of AlGaAs except for an emitter location; depositing emitter contact metal on the AlGaAs at the emitter location; providing an opening to the negative conductivity type layer of gaAs; and depositing collector contact metal on the negative conductivity type layer of GaAs.
Claim 14
Dependent Claim
42 words
The method as claimed in claim 11 wherein the wafer includes a positive conductivity type cap layer on the negative conductivity type layer of AlGaAs, and including the step of etching the cap layer to provide a mesa cap for the HBT.
Claim 15
Dependent Claim
23 words
The method as claimed in claim 11 including the step of implanting protons into the wafer to reduce base-collector capacitance for the HBT.
Claim 16
Dependent Claim
216 words
A self-aligned process for making a double heterojunction bipolar transistor (HBT) comprising; providing a double heterojunction bipolar semiconductor wafer having a top negative conductivity type layer of AlGaAs, an intermediate positive conductivity type layer of GaAs on the negative conductivity type layer of AlGaAs, and a bottom negative conductivity type layer of AlGaAs on the intermediate positive conductivity type layer of GaAs; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the top negative conductivity type layer of AlGaAs through the opening down to the intermediate positive conductivity type layer of GaAs; implanting protons through the opening into the bottom negative conductivity type layer of AlGaAs; depositing base contact metal on the intermediate positive conductivity type layer of GaAs through the opening; depositing dielectric on the base contact metal and on the sidewalls of the opening; lifting off the photoresist with its overlying dielectric and metal while maintaining dielectric on the sidewalls; masking the remaining dielectric and the top negative conductivity type layer of AlGaAs except for an emitter location; depositing emitter contact metal on the AlGaAs at the emitter location; providing an opening to the bottom negative conductivity type layer of AlGaAs and; depositing collector contact metal on the negative conductivity type layer of GaAs.
Claim 17
Dependent Claim
216 words
A self-aligned process for making a double heterojunction bipolar transistor (HBT) comprising; providing a double heterojunction bipolar semiconductor wafer having a top negative conductivity type layer of AlGaAs, an intermediate positive conductivity type layer of GaAs on the negative conductivity type layer of AlGaAs, and a bottom negative conductivity type layer of AlGaAs on the intermediate positive conductivity type layer of GaAs; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the top negative conductivity type layer of AlGaAs through the opening down to the intermediate positive conductivity type layer of GaAs; implanting protons through the opening into the bottom negative conductivity type layer of AlGaAs; depositing base contact metal on the intermediate positive conductivity type layer of GaAs through the opening; depositing dielectric on the base contact metal and on the sidewalls of the opening; lifting off the photoresist with its overlying dielectric and metal while maintaining dielectric on the sidewalls; masking the remaining dielectric and the top negative conductivity type layer of AlGaAs except for an emitter location; depositing emitter contact metal on the AlGaAs at the emitter location; providing an opening to the bottom negative conductivity type layer of AlGaAs and; depositing collector contact metal on the negative conductivity type layer of GaAs.
Claim 18
Dependent Claim
26 words
The method as claimed in claim 14 wherein the wafer includes a positive conductivity type cap layer on the top negative conductivity type layer of AlGaAs.
Claim 19
Dependent Claim
23 words
The method as claimed in claim 15 including the step of etching the cap layer to provide a mesa cap for the HBT.
Claim 20
Dependent Claim
20 words
The method as claimed in claim 15 including the step of implanting protons into the wafer to reduce base-collector capacitance.
Claim 21
Independent Claim
183 words
A method of fabricating a heterojunction bipolar transistor (HBT), comprising: providing a heterojunction bipolar semiconductor wafer having a first layer of a semiconductor of one conductivity type, a second layer of a semiconductor of an opposite conductivity type on the first layer forming a first p-n junction, and a third layer of a semiconductor of the one conductivity type on the second layer forming a second p-n junction, at least one of the p-n junctions being a heterojunction; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the third layer through the opening to the second layer; depositing base contact metal on the second layer through the opening; etching back some of the photoresist; depositing dielectric on the base contact metal; lifting off the photoresist with its overlying dielectric and metal; defining a location for emitter contact metal of the HBT on the third layer; depositing emitter contact metal on the emitter contact location; providing an opening to the first layer, and; depositing collector contact metal on the first layer through the opening.
Claim 22
Independent Claim
183 words
A method of fabricating a heterojunction bipolar transistor (HBT), comprising: providing a heterojunction bipolar semiconductor wafer having a first layer of a semiconductor of one conductivity type, a second layer of a semiconductor of an opposite conductivity type on the first layer forming a first p-n junction, and a third layer of a semiconductor of the one conductivity type on the second layer forming a second p-n junction, at least one of the p-n junctions being a heterojunction; forming a photoresist pattern on the wafer with an opening which defines a base location of the HBT; etching the third layer through the opening to the second layer; depositing base contact metal on the second layer through the opening; etching back some of the photoresist; depositing dielectric on the base contact metal; lifting off the photoresist with its overlying dielectric and metal; defining a location for emitter contact metal of the HBT on the third layer; depositing emitter contact metal on the emitter contact location; providing an opening to the first layer, and; depositing collector contact metal on the first layer through the opening.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1991-03-15 | 1991-09-14 | 1992-03-15 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1995-03-15 | 1995-09-14 | 1996-03-15 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1999-03-15 | 1999-09-14 | 2000-03-15 | $7700.00 | Window Closed / Lapsed |