US4935796A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Device for minimizing parasitic junction capacitances in an insulated collector vertical P-N-P transistor
Assignee: STMicroelectronics SRL
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Filing: 1988-02-08
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Granted: 1990-06-19
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Expires: 2008-02-08
Abstract
Abstract A device for minimizing parasitic junction capacitances in an isolated collector vertical PNP transistor, having a terminal N connected to an epitaxial n layer, comprises a bootstrap circuit including an emitter follower vertical PNP transistor having its emitter and base respectively connected to the terminal of the epitaxial n layer and the collector of the isolated collector transistor; further, a bias resistance is connected between the emitter and one pole of a voltage supply to the emitter follower.
Inventors
- 👤 Maurizio Zuffada
- 👤 Fabrizio Sacchi
- 👤 Paolo Ferrari
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-09 04:36
CPC Classifications
H; H03; H03F; H03F1/00; H03F1/08; H03F1/14
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
123 words
For use with an isolated collector vertical PNP transistor having an emitter terminal, a base terminal, a non-grounded collector terminal, an epitaxial layer, and a p+ region connected to a circuit ground, an apparatus for minimizing effects of a first parasitic junction capacitance between said p+ region and said epitaxial layer, and a second parasitic junction capacitance between said collector and said epitaxial layer, said apparatus comprising: a second PNP transistor having an emitter terminal and a base terminal connected respectively to said epitaxial layer of said isolated collector vertical PNP transistor and to said collector of said isolated collector vertical PNP transistor, and a collector connected to said circuit ground, thereby substantially eliminating effects of said first and second parasitic junction capacitances.
Claim 2
Dependent Claim
123 words
For use with an isolated collector vertical PNP transistor having an emitter terminal, a base terminal, a non-grounded collector terminal, an epitaxial layer, and a p+ region connected to a circuit ground, an apparatus for minimizing effects of a first parasitic junction capacitance between said p+ region and said epitaxial layer, and a second parasitic junction capacitance between said collector and said epitaxial layer, said apparatus comprising: a second PNP transistor having an emitter terminal and a base terminal connected respectively to said epitaxial layer of said isolated collector vertical PNP transistor and to said collector of said isolated collector vertical PNP transistor, and a collector connected to said circuit ground, thereby substantially eliminating effects of said first and second parasitic junction capacitances.
Claim 3
Dependent Claim
106 words
For use with an isolated collector vertical PNP transistor having an emitter terminal, a base terminal, a non-grounded collector terminal, an epitaxial layer, and a p+ region connected to a circuit ground, an apparatus for minimizing effects of a parasitic junction capacitance between said p+ region and said epitaxial layer, said apparatus comprising: a second PNP transistor having an emitter terminal and a base terminal connected respectively to said epitaxial layer of said isolated collector vertical PNP transistor and to said collector of said isolated collector vertical PNP transistor, and a collector connected to said circuit ground, thereby substantially eliminating effects of said parasitic junction capacitance.
Claim 4
Dependent Claim
106 words
For use with an isolated collector vertical PNP transistor having an emitter terminal, a base terminal, a non-grounded collector terminal, an epitaxial layer, and a p+ region connected to a circuit ground, an apparatus for minimizing effects of a parasitic junction capacitance between said p+ region and said epitaxial layer, said apparatus comprising: a second PNP transistor having an emitter terminal and a base terminal connected respectively to said epitaxial layer of said isolated collector vertical PNP transistor and to said collector of said isolated collector vertical PNP transistor, and a collector connected to said circuit ground, thereby substantially eliminating effects of said parasitic junction capacitance.
Claim 5
Dependent Claim
28 words
An apparatus according to claim 2 further comprising a bias resistor connected between one pole of a voltage supply and said emitter terminal of said second PNP transistor.
Claim 6
Dependent Claim
105 words
For use with an isolated collector vertical PNP transistor having an emitter terminal, a base terminal, a non-grounded collector terminal, an epitaxial layer, and a p+ region connected to a circuit groun, an apparatus for minimizing effects of a parasitic junction capacitance between said collector and said epitaxial layer, said apparatus comprising: a second PNP transistor having an emitter terminal and a base terminal connected respectively to said epitaxial layer of said isolated collector vertical PNP transistor and to said collector of said isolated collector vertical PNP transistor, and a collector connected to said circuit ground, thereby substantially eliminating effects of said parasitic junction capacitance.
Claim 7
Dependent Claim
105 words
For use with an isolated collector vertical PNP transistor having an emitter terminal, a base terminal, a non-grounded collector terminal, an epitaxial layer, and a p+ region connected to a circuit groun, an apparatus for minimizing effects of a parasitic junction capacitance between said collector and said epitaxial layer, said apparatus comprising: a second PNP transistor having an emitter terminal and a base terminal connected respectively to said epitaxial layer of said isolated collector vertical PNP transistor and to said collector of said isolated collector vertical PNP transistor, and a collector connected to said circuit ground, thereby substantially eliminating effects of said parasitic junction capacitance.
Claim 8
Dependent Claim
28 words
An apparatus according to claim 4 further comprising a bias resistor connected between one pole of a voltage supply and said emitter terminal of said second PNP transistor.
Claim 9
Dependent Claim
28 words
An apparatus according to claim 1 further comprising a bias resistor connected between one pole of a voltage supply and said emitter terminal of said second PNP transistor.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-06-18 | 1993-12-18 | 1994-06-19 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-06-18 | 1997-12-18 | 1998-06-19 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-06-18 | 2001-12-18 | 2002-06-19 | $7700.00 | Window Closed / Lapsed |