High-speed semiconductor device

Claim 2

A high-speed semiconductor device, comprising: an emitter layer having a conduction band with a first energy level; a base layer formed under said emitter layer and having a conduction band with a second energy level; superlattice means, disposed between said emitter layer and said base layer, carriers tunneling therethrough, said superlattice means comprising: a first potential barrier layer forming a heterojunction with said emitter layer and having a conduction band with a third energy level, said third energy level being higher than said first energy level so that the conduction band of said emitter layer and the conduction band of said first potential barrier layer have a discontinuity therebetween; a quantum well layer forming a heterojunction with said first potential barrier layer and having a fourth conduction band with a fourth energy level, said fourth energy level being lower than said third energy level; and a second barrier layer forming a heterojunction with said quantum well layer and said base layer and having a conduction band with a fifth energy level, said fifth energy level being higher than said fourth and second energy levels; said first and second barrier layers having a thin thickness for tunneling carriers therethrough, and said quantum well layer having a thin thickness so as to have a sub-band therein; a collector semiconductor layer formed under said base layer; and a collector side potential-barrier means disposed between said base layer and said collector semiconductor layer.

Claim 3

A high-speed semiconductor device according to claim 1, wherein when a predetermined bias voltage is applied between said emitter layer and said base layer, the carriers in said emitter layer tunnel through said superlattice means via said sub-band in said quantum well layer and are injected into said base layer, the energy level of said injected carriers is higher than said second energy level.

Claim 4

A high-speed semiconductor device according to claim 1, wherein each of said first and second potential barrier layers and said quantum-well layer are formed with thicknesses of approximately 3˜5 nm (30˜50 Å).

Claim 5

A high-speed semiconductor device according to claim 1, wherein: said superlattice means includes a plurality of quantum-well layer forming means which are stack-formed with a periodical structure; and said superlattice means has at least one conduction minienergy band for tunneling the carriers therethrough.

Claim 6

A high-speed semiconductor device according to claim 1, wherein: said emitter layer is formed of a material selected from the group consisting of GaAs, In x GA 1-x As (0≦x<1), and (In x As 1-x )m(GaAs)n(1<m≲3, 1<n≲3); said first and second barrier layers of said superlattice means are formed of a material selected from the group consisting of (Al x Ga 1-x )As, InP, (In x Al 1-x )As, and Al 2 O 3 ; said quantum well layer is formed of a material selected from the group consisting of GaAs, and (In x GA 1-x )As; said base layer is formed of a material selected from the group consisting of GaAs, (In x Ga 1-x )As, (In x As 1-x )m(GaAs)n, and Al; said potential barrier means is formed of a material selected from the group consisting of (Al x GA 1-x )As, InP, and (In x Al 1-x )As; and said collector layer is formed of a material selected from the group consisting of GaAs, (In x GA 1-x )As, and (InAs) m (GaAs) n .

Claim 7

A high-speed semiconductor device according to claim 1, further comprising a graded layer, disposed between said emitter layer and said superlattice means, having a conduction band with a graded conduction-energy level which is approximately equal to the first energy level of said emitter layer at an interface of said emitter layer and said graded layer, and approximately equal to a predetermined energy level lower than said third energy level of said superlattice means at an interface of said superlattice means and said graded layer, to enable tunneling of the carriers therethrough, the carriers in said emitter layer being transported along said graded conduction-energy level in said graded layer, tunneling through said superlattice means via said sub-band in said quantum well layer, and injected into said base layer.

Claim 8

A high-speed semiconductor device according to claim 6, wherein said graded layer is formed of non-doped Al x Ga 1-x As (0.1≲x≲0.3) and has a thickness of aproximately 10 nm (100 Å).

Claim 9

A high-speed semiconductor device according to claim 2, wherein: when an input pulse signal having a predetermined voltage range, predetermined slope and a predetermined frequency is applied between said base layer and emitter layer, an output signal having a plural multiplied frequency of said predetermined input frequency is provided at said collector layer.

Claim 10

A high-speed semiconductor device according to claim 1, wherein said collector side potential-barrier means comprises a layer forming a heterojunction with said base layer and having a conduction band with a sixth energy level, said sixth energy level being higher than said second energy level, wherein when a predetermined bias voltage is applied between said emitter layer and said base layer, the carriers in said emitter layer tunnel through said superlattice means via said sub-band in said quantum well layer and are injected into said base layer, and wherein an energy difference between an energy level of said injected carriers in said base layer and said second energy level is lower than the energy difference between said sixth energy level and said second energy level.

Claim 11

A high-speed hot electron transistor (HET), comprising: a collector semiconductor layer; a collector side potential barrier layer formed on said collector semiconductor layer having a conduction band with an energy level higher than that of a conduction band of said collector semiconductor layer; a base semiconductor or metal layer formed on said collector side potential barrier layer having a conduction band with an energy level lower than that of the conduction band of said collector side barrier layer; superlattice means formed on said base layer, said superlattice means comprising: a first potential barrier layer formed on said base layer having a conduction band with a higher energy level than that of the conduction band of the base layer, an energy level discontinuity being formed between said first potential layer and said base layer; a quantum well layer formed on said first potential barrier layer having a conduction band; and a second potential barrier layer formed on said quantum well layer having a conduction band with a higher energy level than that of the quantum well layer, said quantum well layer having so thin a thickness that a sub-band is provided therein; and an emitter semiconductor layer formed on said second potential barrier layer having a conduction band with an energy level lower than that of the conduction band of the second potential barrier layer, and an energy level discontinuity being formed between said emitter layer and said second potential barrier layer.

Claim 12

A high-speed hot electron transistor (HET), comprising: a collector semiconductor layer; a collector side potential barrier layer formed on said collector semiconductor layer having a conduction band with an energy level higher than that of a conduction band of said collector semiconductor layer; a base semiconductor or metal layer formed on said collector side potential barrier layer having a conduction band with an energy level lower than that of the conduction band of said collector side barrier layer; superlattice means formed on said base layer, said superlattice means comprising: a first potential barrier layer formed on said base layer having a conduction band with a higher energy level than that of the conduction band of the base layer, an energy level discontinuity being formed between said first potential layer and said base layer; a quantum well layer formed on said first potential barrier layer having a conduction band; and a second potential barrier layer formed on said quantum well layer having a conduction band with a higher energy level than that of the quantum well layer, said quantum well layer having so thin a thickness that a sub-band is provided therein; and an emitter semiconductor layer formed on said second potential barrier layer having a conduction band with an energy level lower than that of the conduction band of the second potential barrier layer, and an energy level discontinuity being formed between said emitter layer and said second potential barrier layer.

Claim 13

A high-speed hot electron transistor (HET), comprising: a semiconductor collector layer formed on a semiconductor substrate having a conduction band with an energy level; a first potential barrier layer formed on said semiconductor collector layer having a conduction band with an energy level higher than that of the conduction band of said collector layer; a base layer formed on said first potential barrier layer having a conduction band with an energy level lower than that of the conduction band of said first potential barrier layer; superlattice means, formed on said base layer comprising: a second potential barrier layer formed on said base layer having a conduction band with a higher energy level than that of the conduction band of said base layer, an energy level discontinuity being formed between said second potential barrier layer and said base layer; a quantum well layer formed on said second potential barrier layer having a conduction band with an energy level; and a third potential barrier layer formed on said quantum well layer having a conduction band with a higher energy level than that of the conduction band of said quantum well layer, said quantum well layer having so thin thickness that a sub-band is provided therein; a graded layer formed on said superlattice means, having a conduction band with a graded conduction-energy level; and an emitter layer formed on said third potential barrier layer having a conduction band with an energy level lower than that of the conduction band of said third potential barrier layer, and an energy level discontinuity being formed between said emitter layer and said third potential barrier layer.

Claim 14

A high-speed hot electron transistor (HET), comprising: a semiconductor collector layer formed on a semiconductor substrate having a conduction band with an energy level; a first potential barrier layer formed on said semiconductor collector layer having a conduction band with an energy level higher than that of the conduction band of said collector layer; a base layer formed on said first potential barrier layer having a conduction band with an energy level lower than that of the conduction band of said first potential barrier layer; superlattice means, formed on said base layer comprising: a second potential barrier layer formed on said base layer having a conduction band with a higher energy level than that of the conduction band of said base layer, an energy level discontinuity being formed between said second potential barrier layer and said base layer; a quantum well layer formed on said second potential barrier layer having a conduction band with an energy level; and a third potential barrier layer formed on said quantum well layer having a conduction band with a higher energy level than that of the conduction band of said quantum well layer, said quantum well layer having so thin thickness that a sub-band is provided therein; a graded layer formed on said superlattice means, having a conduction band with a graded conduction-energy level; and an emitter layer formed on said third potential barrier layer having a conduction band with an energy level lower than that of the conduction band of said third potential barrier layer, and an energy level discontinuity being formed between said emitter layer and said third potential barrier layer.

Claim 15

An HET according to claim 11, wherein the graded conduction-energy level of said graded layer is approximately equal to the energy level of said emitter layer at an interface of said emitter layer and said graded layer, and approximately equal to a predetermined energy level lower than the energy level of said third potential barrier level at an interface of said superlattice means and said graded layer, to enable tunneling of carriers therethrough, carriers in said emitter layer being transported along said graded conduction-energy level in said graded layer, tunneling through said superlattice means via said sub-band in said quantum well layer, and injected into said base layer.