Patent US5239447A successfully refreshed from Google Patents.
US5239447A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Stepped electronic device package
Assignee: International Business Machines Corp
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Filing: 1991-09-13
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Granted: 1993-08-24
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Expires: 2011-09-13
Abstract
Abstract An electronic device packaging structure is described wherein an electronic device is electrically connected to a substrate wherein the electronic device subtends a non-normal angle with respect to the substrate. In a more specific embodiment, a plurality of electronic devices are stacked at offset with respect to each other to expose contact locations on the surface of each electronic device at an edge of each electronic device to form a stepped surface exposing a plurality of electronic device contact locations. This surface is disposed against a substrate having a plurality of contact locations thereon. The electronic device contact locations can be electrically interconnected to the substrate contact locations by solder mounds or alternatively by a cylindrical shaped elastomeric body having metallization bands with a spacing corresponding to the electronic device contact locations. The elastomeric body is pressed between the edge of the stacked electronic devices having the contact locations thereon and substrate surface to form electrical interconnections between electronic device contact locations and substrate contact locations through the electrically conducting bands. The stacked electronic devices can be thermally connected to a heat dissipation member. The stacked electronic devices can have a stepped surface embodying an enhanced area for transfer of heat from the electronic device stack to the heat dissipation member.
Inventors
- 👤 Paul W. Cotues
- 👤 Paul A. Moskowitz
- 👤 Philip Murphy
- 👤 Mark B. Ritter
- 👤 George F. Walker
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-25 08:51
CPC Classifications
H; H05; H05K; H05K3/00; H05K3/36; H05K3/366; H10; H10W; H10W90/00; H05K2201/00; H05K2201/03; H05K2201/0302; H05K2201/0314; H05K2201/10; H05K2201/10431; H05K2201/10439; H05K2201/10484; H05K3/30; H05K3/32; H05K3/325; H05K3/34; H05K3/341; H05K3/3431; H05K3/3442; H10W72/00; H10W72/50; H10W72/541; H10W72/5445; H10W72/547; H10W72/5473; H10W72/551; H10W72/552; H10W72/5522; H10W72/5524; H10W72/5525; H10W72/60; H10W90/20; H10W90/24; H10W90/288; H10W90/291; H10W90/701; H10W90/751; H10W90/752; H10W90/754
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
285 words
A structure comprising: a substrate having a plurality of substrate contact locations thereon; a plurality of semiconducting chips each having a first and second major surface and each having an edge having thereat a plurality of chip contact locations on said first major surface; each of said plurality of chips being disposed against each other so that a first major surface of one of said plurality of chips is disposed against the second major surface on an adjacent chips to form a stack of chips; each of said chips is disposed to have said edge at the same side of said stack; each of said chips is disposed to form a stepped surface to permit said plurality of said chip contact locations to be exposed at said side; said stepped surface having a plurality of adjacent triangular notches one side of which contains chips contact locations and the other side of which is an edge of adjacent chip; said stepped surface is disposed against said substrate so that said chip contact locations are aligned with said plurality of substrate contact locations; an electrical interconnection means for electrically interconnecting said chip contact locations with said plurality of substrate contact locations; said electrical interconnection means comprising a plurality of elongated electrical conductive members embedded in an elastomeric material; said electrical interconnection means being disposed in said notches, at least one of elongated electrically conductive members being aligned and in contact with at least one of said chip contact locations in said notch; and a means for pressing said stack towards said substrate so that at least one of said elongated electrically conductive members is pressed in contact with a chip contact location and a substrate contact location.
Claim 2
Dependent Claim
285 words
A structure comprising: a substrate having a plurality of substrate contact locations thereon; a plurality of semiconducting chips each having a first and second major surface and each having an edge having thereat a plurality of chip contact locations on said first major surface; each of said plurality of chips being disposed against each other so that a first major surface of one of said plurality of chips is disposed against the second major surface on an adjacent chips to form a stack of chips; each of said chips is disposed to have said edge at the same side of said stack; each of said chips is disposed to form a stepped surface to permit said plurality of said chip contact locations to be exposed at said side; said stepped surface having a plurality of adjacent triangular notches one side of which contains chips contact locations and the other side of which is an edge of adjacent chip; said stepped surface is disposed against said substrate so that said chip contact locations are aligned with said plurality of substrate contact locations; an electrical interconnection means for electrically interconnecting said chip contact locations with said plurality of substrate contact locations; said electrical interconnection means comprising a plurality of elongated electrical conductive members embedded in an elastomeric material; said electrical interconnection means being disposed in said notches, at least one of elongated electrically conductive members being aligned and in contact with at least one of said chip contact locations in said notch; and a means for pressing said stack towards said substrate so that at least one of said elongated electrically conductive members is pressed in contact with a chip contact location and a substrate contact location.
Claim 3
Dependent Claim
41 words
The structure of claim 1, wherein said plurality of electronic devices are disposed against adjacent electronic devices of said plurality to form a stack having at least one stepped side exposing a region of the top surfaces of adjacent electronic devices.
Claim 4
Dependent Claim
26 words
The structure of claim 2, further including a heat dissipation means having a stepped surface to engage said at least one stepped side of said stack.
Claim 5
Dependent Claim
17 words
The structure of claim 1, further including a means to hold said electronic devices in said stack.
Claim 6
Dependent Claim
24 words
The structure of claim 4, wherein said means to hold said electronic devices in said stack is an adhesive disposed between adjacent electronic devices.
Claim 7
Dependent Claim
20 words
The structure of claim 4, wherein said means to hold said electronic devices in said stack is a mechanical clamp.
Claim 8
Dependent Claim
17 words
The structure of claim 1, further including a heat dissipation means in thermal contact with said stack.
Claim 9
Dependent Claim
21 words
The structure of claim 1, wherein said electronic devices are semiconducting chips and wherein said substrate is an electronic packaging substrate.
Claim 10
Dependent Claim
284 words
A structure comprising: a substrate having a plurality of substrate contact locations thereon; a plurality of semiconducting chips each having a first and second major surface and each having an edge having in the vicinity thereof plurality of chip contact locations on said first major surface; each of said plurality of chips being disposed adjacent each other so that a first major surface of one of said plurality of chips is disposed adjacent the second major surface of an adjacent chips to form a stack of chips; each of said chips is disposed to have said edge at the same side of said stack; each of said chips is disposed to form a stepped surface to permit said plurality of said chip contact locations to be exposed at said side; said stepped surface having a plurality of adjacent triangular notches one side of which contains chips contact locations and the other side of which is an edge of an adjacent chip; said stepped surface is disposed against said substrate so that said chip contact locations are aligned with said plurality of substrate contact locations; an electrical interconnection means for electrically interconnecting said chip contact locations with said plurality of substrate contact locations; said electrical interconnection means comprising a clestomeric dielectric body having a plurality of bands of electrically conductive material; said electrical interconnection means being disposed in said notches, at least one of said bands being aligned and in contact with at least one of said chip contact locations in said notch; and a means for pressing said stack towards said substrate so that at least one of said bands is pressed in contact with a chip contact location and a substrate contact location.
Claim 11
Dependent Claim
284 words
A structure comprising: a substrate having a plurality of substrate contact locations thereon; a plurality of semiconducting chips each having a first and second major surface and each having an edge having in the vicinity thereof plurality of chip contact locations on said first major surface; each of said plurality of chips being disposed adjacent each other so that a first major surface of one of said plurality of chips is disposed adjacent the second major surface of an adjacent chips to form a stack of chips; each of said chips is disposed to have said edge at the same side of said stack; each of said chips is disposed to form a stepped surface to permit said plurality of said chip contact locations to be exposed at said side; said stepped surface having a plurality of adjacent triangular notches one side of which contains chips contact locations and the other side of which is an edge of an adjacent chip; said stepped surface is disposed against said substrate so that said chip contact locations are aligned with said plurality of substrate contact locations; an electrical interconnection means for electrically interconnecting said chip contact locations with said plurality of substrate contact locations; said electrical interconnection means comprising a clestomeric dielectric body having a plurality of bands of electrically conductive material; said electrical interconnection means being disposed in said notches, at least one of said bands being aligned and in contact with at least one of said chip contact locations in said notch; and a means for pressing said stack towards said substrate so that at least one of said bands is pressed in contact with a chip contact location and a substrate contact location.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-08-23 | 1997-02-22 | 1997-08-24 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-08-23 | 2001-02-22 | 2001-08-24 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-08-23 | 2005-02-22 | 2005-08-24 | $7700.00 | Window Closed / Lapsed |