Low temperature electronic package having a superconductive interposer for interconnecting strip type circuits

Claim 2

A multidimensional package for a first circuit-bearing substrate and a second circuit-bearing substrate, each having a conductor pattern providing electrical connection to its circuits, and each having an insulated ground plane characterized by (a) an interposer of crystalline substrate material in continuous angle-free cross section bearing an arcuate insulated ground plane and an arcuate pattern of conductors overlying said insulated ground plane; (b) first connector means selectively connecting the conductor pattern of the first substrate to the conductor pattern of said interposer; and (c) second connector means selectively connecting the arcuate conductor pattern of said interposer to the conductor pattern of said second substrate; and further characterized in that the first substrate, the second substrate and said interposer are all comprised of crystalline substrate materials having essentially the same coefficient of thermal expansion.

Claim 3

A circuit package according to claim 1 further characterized in that said crystalline substrate materials having the same characteristic of thermal expansion are of semiconductor grade silicon.

Claim 4

A circuit package according to claim 1 further characterized in that the conductor patterns on the first and second substrates, the conductor pattern on said interposer, the ground planes on the first and second substrates, and said insulated ground-plane layer are electrical conductors and said connector means comprise electrically conducting solders having differing melting points to that of the arcuate pattern of conductors and patterns of conductors on the first and second substrate.

Claim 5

A circuit package according to claim 3 further characterized in that said first connector means has a melting point differing from the melting point of said second connector means.

Claim 6

A circuit package according to claim 4 further characterized in that said electrical conductors are superconductive at cryogenic temperatures.

Claim 7

A multidimensional package according to claim 1 further characterized in that the first substrate conductor pattern carries a circuit array having conductive striplines spaced, in at least one critical area, near the minimum linear spacing within lithographic tolerances; the second substrate conductor pattern carries a circuit array having conductive striplines spaced, in at least one critical area, near the minimum linear spacing within lithographic tolerances; said interposer arcuate conductor pattern carries a circuit array having conductive striplines spaced, in at least one critical area, near the minimum linear spacing within lithographic tolerances; said first substrate means, said second substrate means and said interposer means all of crystalline substrate material; said first connector means comprises a first array of connection pads carried by said first substrate and, terminating respective ends of conductive striplines on the first substrate, said pads being spaced apart in echelons at distances significantly greater than the minimum linear spacing within lithographic tolerances; said second connector means comprises a second array of connection pads carried by said second substrate and terminating respective ends of conductive striplines on the second substrate, said pads being spaced apart in echelons at distances significantly greater than the minimum linear spacing within lithographic tolerances; said interposer comprises a third array of connection pads terminating first ends of respective conductive striplines on said interposer, said pads being spaced apart in echelons at distances significantly greater than the minimum linear spacing within lithographic tolerances; said interposer comprises a fourth array of connection pads terminating respective conductive striplines on said interposer at the end opposite said third array of connection pads, said pads being spaced apart in echelons at distances significantly greater than the minimum linear spacing within lithographic tolerances; and further characterized by array connection means for connecting said first array of connection pads to said third array of connection pads, respectively, and for connecting said second array of connection pads to said fourth array of connection pads, respectively.

Claim 8

A multidimensional package according to claim 6, further characterized in that the first and second substrate and said interposer each have a ground plane insulated from and underlying the circuit arrays, which with conductive striplines forms transmission lines further characterized by ground plane connection means for providing at a number of points an electrical connection of first substrate ground plane to interposer ground plane to second substrate ground plane whereby the equivalent circuit for a representative circuit connection includes transmission line, small inductance at the discontinuity of the array connection, transmission line, small inductance at the discontinuity of the array connection, transmission line.

Claim 9

Circuit connection mechanism according to claim 7 further characterized in that said connection interposer means is a rounded corner flat-sided rod carrying on one flat side said third array of connection pads as a two-dimensional array of connection pads including circuit connection pads and ground plane connection pads, and carrying on another flat side said fourth array of connection pads as a two-dimensional array of connection pads including circuit connection pads and ground plane connection pads.

Claim 10

A multidimensional packaging technique for a first circuit-bearing substrate and a second circuit-bearing substrate, each having a conductor pattern providing electrical connection to its circuits, and each having an insulated ground plane characterized by (a) an interposer of crystalline substrate material in continuous angle-free cross section bearing an arcuate insulated ground plane and an arcuate pattern of conductors overlying said insulated ground plane; (b) first connector means selectively connecting the conductor pattern of the first substrate to the conductor pattern of said interposer; and (c) second connector means selectively connecting the arcuate conductor pattern of said interposer to the conductor pattern of said second substrate, further characterized by (d) third connector means connecting said arcuate insulated ground plane to the insulated ground planes of the first and second circuit-bearing substrates at a number of points dispersed over areas of close approach of substrate ground plane to arcuate ground plane, and further characterized in that said first, second and third connector means are controlled collapse connectors.

Claim 11

A multidimensional packaging technique for a first circuit-bearing substrate and a second circuit-bearing substrate, each having a conductor pattern providing electrical connection to its circuits, and each having an insulated ground plane characterized by (a) an interposer of crystalline substrate material in continuous angle-free cross section bearing an arcuate insulated ground plane and an arcuate pattern of conductors overlying said insulated ground plane; (b) first connector means selectively connecting the conductor pattern of the first substrate to the conductor pattern of said interposer; and (c) second connector means selectively connecting the arcuate conductor pattern of said interposer to the conductor pattern of said second substrate, further characterized by (d) third connector means connecting said arcuate insulated ground plane to the insulated ground planes of the first and second circuit-bearing substrates at a number of points dispersed over areas of close approach of substrate ground plane to arcuate ground plane, and further characterized in that said first, second and third connector means are controlled collapse connectors.