US4296456A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Electronic package for high density integrated circuits
Assignee: Samsung Electronics Co Ltd
•
Filing: 1980-06-02
•
Granted: 1981-10-20
•
Expires: 2000-06-02
Abstract
Abstract The present disclosure describes a multi-layered integrated circuit package especially suited for high density circuit applications, such as those involving LSI or ULSI. The package is characterized by short uninterrupted electrical circuit paths between the integrated circuit chip and an interconnection medium. The use of metallized vias or feed-throughs commonly employed in multi-layered packages have been eliminated. Also, heat dissipation is enhanced by the short thermal path between the chip and the outer package surface. Finally, the signal lead configuration permits the area occupied by the package on the interconnection medium to be significantly less than that of present-day packages having approximately the same number of input/output pins or terminals.
Inventors
- 👤 Gilbert R. Reid
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:26
CPC Classifications
H; H10; H10W; H10W70/00; H10W70/60; H10W70/67; H10W70/68; H10W70/685; H10W76/00; H10W76/10; H10W76/12; H10W76/15; H10W76/157; H10W70/682; H10W72/00; H10W72/071; H10W72/075; H10W72/07551; H10W72/07554; H10W72/50; H10W72/531; H10W72/5363; H10W72/5366; H10W72/541; H10W72/547
Claims Analysis
Total Claims: 8
Claim 1
Independent Claim
263 words
An electronic package for an integrated circuit chip having a plurality of signal pads along its periphery comprising: a base member and at least a first and a second circuit layer, said first circuit layer being mounted on said base member and said second circuit layer being mounted on said first circuit layer, each of said circuit layers being frame-like and having a central opening, a plurality of electrically conductive chip-connection tabs disposed on a planar surface of each of said circuit layers and situated adjacent the periphery of its central opening, respective pluralities of electrically conductive pin-mounting pads and metallized lines disposed on said planar surface of each of said circuit layers, each of said lines connecting a chip-connection tab to a pin-mounting pad on a common circuit layer; the dimensions of the central opening of said second circuit layer being greater than those of the central opening of said first circuit layer, and the area of the planar surface of said second circuit layer being less than that of said first circuit layer, whereby the chip-mounting tabs and the pin-mounting pads of said first circuit layer remain uncovered in the presence of the mounted second circuit layer; a plurality of input/output pins affixed respectively to the plurality of pin-mounting pads on each of said circuit layers; the central openings of said circuit layers forming a well for receiving said chip, the latter being adapted to be mounted on said base member and to have said signal pads connected respectively to said chip-connection tabs on both said first and second circuit layers.
Claim 2
Dependent Claim
263 words
An electronic package for an integrated circuit chip having a plurality of signal pads along its periphery comprising: a base member and at least a first and a second circuit layer, said first circuit layer being mounted on said base member and said second circuit layer being mounted on said first circuit layer, each of said circuit layers being frame-like and having a central opening, a plurality of electrically conductive chip-connection tabs disposed on a planar surface of each of said circuit layers and situated adjacent the periphery of its central opening, respective pluralities of electrically conductive pin-mounting pads and metallized lines disposed on said planar surface of each of said circuit layers, each of said lines connecting a chip-connection tab to a pin-mounting pad on a common circuit layer; the dimensions of the central opening of said second circuit layer being greater than those of the central opening of said first circuit layer, and the area of the planar surface of said second circuit layer being less than that of said first circuit layer, whereby the chip-mounting tabs and the pin-mounting pads of said first circuit layer remain uncovered in the presence of the mounted second circuit layer; a plurality of input/output pins affixed respectively to the plurality of pin-mounting pads on each of said circuit layers; the central openings of said circuit layers forming a well for receiving said chip, the latter being adapted to be mounted on said base member and to have said signal pads connected respectively to said chip-connection tabs on both said first and second circuit layers.
Claim 3
Dependent Claim
68 words
An electronic package as defined in claim 1 characterized in that the overall dimensions of said first circuit layer are substantially the same as those of said base member and the overall dimensions of said second layer are less than those of said first circuit layer, the respective geometrical centers of said base member and said first and second layers being in substantial alignment along a common axis.
Claim 4
Dependent Claim
57 words
An electronic package as defined in claim 1 further characterized in that the respective overall dimensions of said first and second circuit layers and said base member are substantially the same, said second circuit layer having a plurality of apertures homologously disposed with respect to the pin-mounting pads of said first circuit layer and permitting access thereo.
Claim 5
Dependent Claim
25 words
An electronic package as defined in claim 2 characterized in that said base member and said first and second circuit layers are formed of ceramic.
Claim 6
Dependent Claim
32 words
An electronic package as defined in claim 3 characterized in that said base member is formed of a thermally conductive material and said first and second circuit layers are printed circuit boards.
Claim 7
Dependent Claim
44 words
An electronic package as defined in claims 2 or 3 further including a metallized seal ring mounted on said second circuit layer alongside the chip-connection tabs on said last mentioned layer, and a lid disposed on said ring for providing protection for said chip.
Claim 8
Dependent Claim
28 words
An electronic package as defined in claim 6 wherein said base member, said first and second circuit layers and their respective central openings are all rectangular in form.
References Cited (Backward Citations)
US3354394A
Cited
US3374537A
Cited
US3337678A
Cited
US3550766A
Cited
US3676748A
Cited
US3701964A
Cited
US3760090A
Cited
US3809797A
Cited
US3781596A
Cited
US4164003A
Cited
US4225900A
Cited
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1984-10-19 | 1985-04-20 | 1985-10-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1988-10-19 | 1989-04-20 | 1989-10-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1992-10-19 | 1993-04-20 | 1993-10-20 | $7700.00 | Window Closed / Lapsed |