Data sense circuit for a semiconductor nonvolatile memory device

Claim 1

A non-volatile semiconductor memory device comprising: first and second memory cell arrays, each of said first and second memory cell arrays comprising a plurality of nonvolatile memory cells arranged in respective corresponding row and column matrices; row decoder means for decoding a row address signal and selecting a row of memory cells in said first and second memory cell arrays; first column selection transistors, each first column selection transistor having a gate, a first terminal coupled to a corresponding column of memory cells in said first memory cell array, and a second terminal coupled to a first common connection node; second column selection transistors, each second column selection transistor having a gate, a first terminal coupled to a corresponding column of memory cells in said second memory cell array, and a second terminal coupled to a second common connection node; column decoder means for decoding a column address signal and selecting one of said first column selecting transistors and one of said second column selection transistors by supplying a selection signal to the respective gates thereof; first clamping transistors for clamping a column potential, each first clamping transistor having a first terminal coupled to a corresponding column of memory cells, a second terminal coupled to a power source Vcc, and a gate supplied with a bias potential lower than the potential of said power source Vcc; second clamping transistors for clamping a column potential, each of said second clamping transistors having a first terminal coupled to one of said common connection nodes, a second terminal coupled to the power source Vcc, and a gate supplied with said bias potential; first precharge means responsive to a precharge signal for precharging each column of memory cells in said first and second memory cell arrays to a predetermined potential lower than said power supply Vcc; sense amplifier means having a first input node connected to the first common connection node of said first column selection transistors, a second input node connected to the second common connection node of said second column selection transistors, and first and second output nodes, said sense amplifier sensing and amplifying data read out from memory cells in said first and second memory cell arrays selected by said row and column decoder means; load means for loading the first and second input nodes of said sense amplifier, said load means including a first transistor having a gate supplied with the bias potential and a current path connected between said first input node and said power supply Vcc and a second transistor having a gate supplied with the bias potential and a current path connected between said second input node and said power supply Vcc; second precharge means responsive to the precharge signal for precharging the first and second input nodes of said sense amplifier to a predetermined potential lower than said power supply Vcc; first equalizing means responsive to an equalizes signal for equalizing a potential of the first and second input nodes of said sense amplifier; second equalizing means responsive to the equalizes signal for equalizing potentials of column lines coupled to said first memory cell array and column lines coupled to said second memory cell array; third equalizing means responsive to the equalizes signal for equalizing a potential of the first and second output nodes of said sense amplifier; and a control circuit for generating the equalize signal and the precharge signal in response to one or the other of an address transition signal and a memory selection signal, said control circuit controlling said first, second, and third equalizing means with the equalize signal and controlling said first and second precharging means with the precharge control signal, wherein the precharge signal and the equalize signal are inverted with respect to each other.