US4903235A
Expired / Lapsed
US
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Semiconductor memory
Assignee: Hitachi Ltd
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Filing: 1989-05-09
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Granted: 1990-02-20
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Expires: 2009-05-09
Abstract
Abstract A semiconductor memory includes an array of memory cells wherein each memory cell is disposed at the intersection between a word line and a data line. An output line of the memory is coupled to the data line via transfer MOSFET and a data line signal detecting circuit, the latter being provided between the common data line and the output line. A precharging circuit for precharging the data line and a feedback circuit for coupling together the output and input sides of the data line signal detecting circuit are provided.
Inventors
- 👤 Taei Kubota
- 👤 Tetsuo Nakano
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-02 22:41
CPC Classifications
G; G11; G11C; G11C17/00; G11C17/14; G11C17/16
Claims Analysis
Total Claims: 7
Claim 1
Independent Claim
148 words
A semiconductor memory comprising: a word line; a plurality of data lines; a plurality of memory cells each of which is disposed at an intersection between said word line and one of said data lines; a common data line; a plurality of first MOSFETs each of which has a first conductivity type and is coupled between one of said data lines and said common data line; selecting means coupled to said first MOSFETs and including means for controlling the operation of each of said first MOSFETs; amplifier means coupled to said common data line and including means for providing an output signal having an inverted level with respect to an signal on said common data line; and a second MOSFET having a second conductivity type, coupled to said common data line and responsive to said output signal for providing a predetermined voltage level to said common data line.
Claim 2
Dependent Claim
148 words
A semiconductor memory comprising: a word line; a plurality of data lines; a plurality of memory cells each of which is disposed at an intersection between said word line and one of said data lines; a common data line; a plurality of first MOSFETs each of which has a first conductivity type and is coupled between one of said data lines and said common data line; selecting means coupled to said first MOSFETs and including means for controlling the operation of each of said first MOSFETs; amplifier means coupled to said common data line and including means for providing an output signal having an inverted level with respect to an signal on said common data line; and a second MOSFET having a second conductivity type, coupled to said common data line and responsive to said output signal for providing a predetermined voltage level to said common data line.
Claim 3
Dependent Claim
21 words
A semiconductor memory according to claim 1, further comprising: precharge means for precharging each of said data lines at predetermined level.
Claim 4
Dependent Claim
189 words
A semiconductor memory comprising: a word line; a plurality of data lines; a reference line; a plurality of memory cells each of which is disposed at an intersection between said word line and one of said data lines, wherein at least one memory cell includes a first MOSFET having a gate electrode coupled to said word line, a first electrode coupled to a corresponding data line and a second electrode coupled to said reference line; a common data line; a plurality of second MOSFETs each of which has a first conductivity type and is coupled between each of said data lines and said common data line; selecting means coupled to said second MOSFETs and including means for controlling the operation of each of said second MOSFETs; amplifier means coupled to said common data line and including means for providing an output signal which has an inverted level with respect to a signal on said common data line; and a third MOSFET having a second conductivity type, coupled to said common data line and responsive to said output signal for providing a predetermined voltage level to said common data line.
Claim 5
Dependent Claim
189 words
A semiconductor memory comprising: a word line; a plurality of data lines; a reference line; a plurality of memory cells each of which is disposed at an intersection between said word line and one of said data lines, wherein at least one memory cell includes a first MOSFET having a gate electrode coupled to said word line, a first electrode coupled to a corresponding data line and a second electrode coupled to said reference line; a common data line; a plurality of second MOSFETs each of which has a first conductivity type and is coupled between each of said data lines and said common data line; selecting means coupled to said second MOSFETs and including means for controlling the operation of each of said second MOSFETs; amplifier means coupled to said common data line and including means for providing an output signal which has an inverted level with respect to a signal on said common data line; and a third MOSFET having a second conductivity type, coupled to said common data line and responsive to said output signal for providing a predetermined voltage level to said common data line.
Claim 6
Dependent Claim
22 words
A semiconductor memory according to claim 3, further comprising: precharge means for precharging each of said data lines at a predetermined level.
Claim 7
Dependent Claim
16 words
A semiconductor memory according to claim 4, wherein said first MOSFET has said first conductivity type.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1993-02-19 | 1993-08-21 | 1994-02-20 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1997-02-19 | 1997-08-21 | 1998-02-20 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2001-02-19 | 2001-08-21 | 2002-02-20 | $7700.00 | Window Closed / Lapsed |