Semiconductor memory device with dummy word line/sense amplifier activation

Claim 2

A semiconductor memory device comprising: a plurality of semiconductor memory cells; at least one word line coupled to said plurality of semiconductor memory cells for selectively transmitting an access signal thereto; at least one pair of data lines coupled to said plurality of semiconductor memory cells for transferring data with respect thereto; sense amplifier means coupled to said at least one pair of data lines for amplifying a data signal transferred therethrough; a dummy word line having a signal transfer property corresponding to that of said at least one word line; a dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an addressing operation is effected; and energizing signal generating means coupled to said dummy word line for generating a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier means in response to a dummy selection signal transmitted through said dummy word line.

Claim 3

A semiconductor memory device according to claim 1, wherein said energizing signal generating means is connected to produce a second energizing signal for a preset period of time to activate said sense amplifier means in response to the trailing edge of a write-in mode setting signal which is generated after said first energizing signal in a write-in operation cycle.

Claim 4

A semiconductor memory device according to claim 1, which further comprises capacitive means coupled to said dummy word line.

Claim 5

A semiconductor memory device according to claim 3, wherein said capacitive means includes at least one MOS capacitor.

Claim 6

A semiconductor memory device according to claim 1, 2 or 3, which further comprises a column decoder for selectively energizing said at least one pair of data lines, and a pair of input/output lines coupled to said at least one pair of data lines through said column decoder.

Claim 7

A semiconductor memory device according to claim 5, wherein said sense amplifier means includes a sense amplifier having an input/output terminal coupled to said input/output lines for amplifying a data signal on said input/output lines in response to an output signal from said energizing signal generating means.

Claim 8

A semiconductor memory device according to claim 1, 2 or 3, which further comprises a means coupled to said at least one pair of data lines for setting said data lines to an equal potential level every time when an address designating operation is effected.

Claim 9

A semiconductor memory device according to claim 1, 2 or 3, wherein said sense amplifier means includes at least one sense amplifier having input/output terminals coupled to said at least one pair of data lines for amplifying a data signal on said at least one pair of data lines in response to an output signal from said energizing signal generating means.

Claim 10

A semiconductor memory device according to claim 1, 2 or 3, wherein said dummy word line is made of substantially the same semiconductor material as that of said at least one word line.

Claim 11

A semiconductor memory device according to claim 1, 2 or 3, which further comprises decoding means for selectively energizing said at least one word line, said decoding means and said dummy selection signal generating means having approximately the same response time characteristic.

Claim 12

A semiconductor memory device comprising: a plurality of semiconductor memory cells arranged in a matrix array; a plurality of word lines each commonly coupled to the semiconductor memory cells on the same row; a plurality of pairs of data lines each pair commonly coupled to the semiconductor memory cells on the same column for the transfer of data with respect to these memory cells; sense amplifier means coupled to said plurality of pairs of data lines for amplifying data transferred through one of said data line pairs; a dummy word line having a signal transfer property corresponding to those of said word lines; dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an address designating operation is effected; and energizing signal generating means, coupled to said dummy word line for producing a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier means in response to a dummy selection signal transmitted through said dummy word line.

Claim 13

A semiconductor memory device comprising: a plurality of semiconductor memory cells arranged in a matrix array; a plurality of word lines each commonly coupled to the semiconductor memory cells on the same row; a plurality of pairs of data lines each pair commonly coupled to the semiconductor memory cells on the same column for the transfer of data with respect to these memory cells; sense amplifier means coupled to said plurality of pairs of data lines for amplifying data transferred through one of said data line pairs; a dummy word line having a signal transfer property corresponding to those of said word lines; dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an address designating operation is effected; and energizing signal generating means, coupled to said dummy word line for producing a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier means in response to a dummy selection signal transmitted through said dummy word line.

Claim 14

A semiconductor memory device according to claim 11, wherein said energizing signal generating means is connected to produce a second energizing for a preset period of time to activate said sense amplifier means in response to the trailing edge of a write-in mode setting signal which is generated after said first energizing signal in a write-in operation cycle.

Claim 15

A semiconductor memory device according to claim 11, which further comprises capacitive means coupled to said dummy word line.

Claim 16

A semiconductor memory device according to claim 13, wherein said capacitive means includes at least one MOS capacitor.

Claim 17

A semiconductor memory device according to claim 11, 12 or 13, which further comprises decoding means for selectively energizing said plurality of pairs of data lines and a pair of input/output lines coupled to said plurality of pairs of data lines through said decoding means.

Claim 18

A semiconductor memory device according to claim 15, wherein said sense amplifier means includes a sense amplifier having input/output terminals coupled to said pair of input/output lines for amplifying a data signal on said input/output lines in response to an output signal from said energizing signal generating means.

Claim 19

A semiconductor memory device according to claim 11, 12 or 13, which further comprises means coupled to said plurality of pairs of data lines for setting said data lines to an equal potential level every time when an address specifying operation is effected.

Claim 20

A semiconductor memory device according to claim 11, 12 or 13, wherein said sense amplifier means includes a plurality of sense amplifiers each having input/output terminals coupled to said plurality of pairs of data lines for amplifying a data signal on the corresponding pair of data lines in response to an output signal from said energizing signal generating means.

Claim 21

A semiconductor memory device according to claim 11, 12 or 13, wherein said dummy word line is made of substantially the same semiconductor material as said word lines.

Claim 22

A semiconductor memory device according to claim 11, 12 or 13, wherein said dummy word line extends substantially parallel to said word lines.

Claim 23

A semiconductor memory device according to claim 11, 12 or 13, which further comprises a decoding means for selectively energizing said plurality of word lines, said decoding means and said dummy selection signal generating means having approximately the same response time characteristics.

Claim 24

A semiconductor memory device comprising: a plurality of semiconductor memory cells arranged in a matrix array; a plurality of word lines each commonly coupled to the semiconductor memory cells in each row of said matrix array; a plurality of data lines each commonly coupled to the semiconductor memory cells in each column of said matrix array for the transfer of data with respect to these memory cells; a sense amplifier means coupled to said plurality of data lines for amplifying data transferred through one of said data lines; a dummy word line having a signal transfer property corresponding to those of said word lines; a dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an address designating operation is effected; and energizing signal generating means coupled to said dummy word line for producing a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier in response to a dummy selection signal transmitted through said dummy word line.

Claim 25

A semiconductor memory device comprising: a plurality of semiconductor memory cells arranged in a matrix array; a plurality of word lines each commonly coupled to the semiconductor memory cells in each row of said matrix array; a plurality of data lines each commonly coupled to the semiconductor memory cells in each column of said matrix array for the transfer of data with respect to these memory cells; a sense amplifier means coupled to said plurality of data lines for amplifying data transferred through one of said data lines; a dummy word line having a signal transfer property corresponding to those of said word lines; a dummy selection signal generating means coupled to said dummy word line for supplying a dummy selection signal to said dummy word line every time an address designating operation is effected; and energizing signal generating means coupled to said dummy word line for producing a first energizing signal for a preset period of time in each operation cycle to activate said sense amplifier in response to a dummy selection signal transmitted through said dummy word line.

Claim 26

A semiconductor memory device according to claim 22, wherein said energizing signal generating means is connected to produce a second energizing for a preset period of time to activate said sense amplifier means in response to the trailing edge of a write-in mode setting signal which is generated after said first energizing signal in a write-in operation cycle.

Claim 27

A semiconductor memory device according to claim 22, which further comprises at least one dummy data line coupled to said sense amplifier means and at least one dummy memory cell coupled to said at least one dummy word line for supplying a dummy data to said dummy data line in response to a first energizing signal supplied from said energizing signal generating means through said dummy word line.

Claim 28

A semiconductor memory device according to claim 22, 23 or 24, wherein said dummy word line is made practically of the same semiconductor material as that of said word lines.

Claim 29

A semiconductor memory device according to claim 22, 23 or 24, wherein said dummy word line extends substantially parallel to said word lines.

Claim 30

A semiconductor memory device according to claim 22, 23 or 24, which further comprises decoding means for selectively energizing said plurality of word lines, said decoding means and said dummy selection signal generating means having practically the same response time characteristics.