Nonvolatile memory circuit device with low power consumption and wide operating voltage range

Claim 2

A nonvolatile memory circuit device comprising: a memory cell array having a plurality of memory cells formed of nonvolatile transistors; a plurality of column lines connected to drains of said memory cells; a plurality of column selection transistors respectively connected at one end to said column lines and commonly connected at the other end to a first node; a precharging transistor of a first conductivity type operated by a precharge signal, and connected between a first potential terminal and said first node; at least one discharging transistor of a second conductivity type connected between a second potential terminal and sources of said memory cells, said discharging transistor being operated by the precharge signal; potential supplying means for selectively supplying a potential lower than the first potential at said first potential terminal to gates of said column selection transistors according to address input; and a sense amplifier connected to said first node.

Claim 3

A nonvolatile memory circuit device according to claim 1, wherein said sense amplifier includes a flip-flop formed of a CMOS logic gate circuit for comparing the potential at said fist node with a reference potential.

Claim 4

A nonvolatile memory circuit device according to claim 1, wherein said device further comprises a power source terminal, and said potential supplying means includes a constant potential circuit for delivering said potential held at a constant value irrespective of a variation of an output voltage at said power source terminal.

Claim 5

A nonvolatile memory circuit device comprising: a memory cell array having a plurality of memory cells formed of nonvolatile transistors; a plurality of column lines connected to drains of said memory cells; a plurality of column selection transistors respectively connected at one end to said column lines and commonly connected at the other end to a first node; a precharging transistor of a first conductivity type operated by a precharge signal, and connected between a first potential terminal and a second node; at least one discharging transistor of a second conductivity type connected between a second potential terminal and sources of said memory cells, said discharging transistor being operated by the precharge signal; a level-down transistor of the second conductivity type which is connected between said first and second nodes and whose gate is supplied with a potential lower than the potential at said first potential terminal in the data readout mode; and a sense amplifier connected to said second node.

Claim 6

A nonvolatile memory circuit device comprising: a memory cell array having a plurality of memory cells formed of nonvolatile transistors; a plurality of column lines connected to drains of said memory cells; a plurality of column selection transistors respectively connected at one end to said column lines and commonly connected at the other end to a first node; a precharging transistor of a first conductivity type operated by a precharge signal, and connected between a first potential terminal and a second node; at least one discharging transistor of a second conductivity type connected between a second potential terminal and sources of said memory cells, said discharging transistor being operated by the precharge signal; a level-down transistor of the second conductivity type which is connected between said first and second nodes and whose gate is supplied with a potential lower than the potential at said first potential terminal in the data readout mode; and a sense amplifier connected to said second node.

Claim 7

A nonvolatile memory circuit device according to claim 4, wherein said sense amplifier includes comparator means having a flip-flop formed of a CMOS logic gate circuit for comparing the potential at said second node with a reference potential.

Claim 8

A nonvolatile memory circuit device according to claim 4, wherein said device further comprises a power source terminal and a potential supplying means connected to said power source terminal, said potential supplying means supplying said potential held at a constant value irrespective of a variation of an output voltage at said power source terminal.

Claim 9

A nonvolatile memory circuit device comprising: a memory cell array having a plurality of memory cells formed of nonvolatile transistors; a plurality of column lines connected to drains of said memory cells; a plurality of column selection transistors respectively connected at one end to said column lines and commonly connected at the other end to a first node; a precharging transistor of a first conductivity type, which is turned on by a precharge signal to increase the potential of a bit line connected to each memory cell to a predetermined potential level, connected between a first potential terminal and said first node; at least one discharging transistor of a second conductivity type, which is turned off by said precharge signal to discharge said potential of said bit line, connected between a second potential terminal and sources of said memory cells; potential supplying means for selectively supplying a potential lower than the first potential at said first potential terminal to gates of said column selection transistors according to address input; and a sense amplifier connected to said first node.

Claim 10

A nonvolatile memory circuit device comprising: a memory cell array having a plurality of memory cells formed of nonvolatile transistors; a plurality of column lines connected to drains of said memory cells; a plurality of column selection transistors respectively connected at one end to said column lines and commonly connected at the other end to a first node; a precharging transistor of a first conductivity type, which is turned on by a precharge signal to increase the potential of a bit line connected to each memory cell to a predetermined potential level, connected between a first potential terminal and said first node; at least one discharging transistor of a second conductivity type, which is turned off by said precharge signal to discharge said potential of said bit line, connected between a second potential terminal and sources of said memory cells; potential supplying means for selectively supplying a potential lower than the first potential at said first potential terminal to gates of said column selection transistors according to address input; and a sense amplifier connected to said first node.

Claim 11

A nonvolatile memory circuit device comprising: a memory cell array having a plurality of memory cells formed of nonvolatile transistors; a plurality of column lines connected to drains of said memory cells; a plurality of column selection transistors respectively connected at one end to said column lines and commonly connected at the other end to a first node; a precharging transistor of a first conductivity type, which is turned on by a precharge signal to increase the potential of a bit line connected to each memory cell to a predetermined potential level, connected between a first potential terminal and a second node; at least one discharging transistor of a second conductivity type, which is turned off by said precharge signal to discharge said potential of said bit line, connected between a second potential terminal and sources of said memory cells; a level-down transistor of the second conductivity type which is connected between said first and second nodes and whose gate is supplied with a potential lower than the potential at said first potential terminal in the data readout mode; and a sense amplifier connected to said second node.

Claim 12

A nonvolatile memory circuit device comprising: a memory cell array having a plurality of memory cells formed of nonvolatile transistors; a plurality of column lines connected to drains of said memory cells; a plurality of column selection transistors respectively connected at one end to said column lines and commonly connected at the other end to a first node; a precharging transistor of a first conductivity type, which is turned on by a precharge signal to increase the potential of a bit line connected to each memory cell to a predetermined potential level, connected between a first potential terminal and a second node; at least one discharging transistor of a second conductivity type, which is turned off by said precharge signal to discharge said potential of said bit line, connected between a second potential terminal and sources of said memory cells; a level-down transistor of the second conductivity type which is connected between said first and second nodes and whose gate is supplied with a potential lower than the potential at said first potential terminal in the data readout mode; and a sense amplifier connected to said second node.