Dry process for removal of undesirable oxide and/or silicon residues from semiconductor wafer after processing

Claim 2

In a process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement which comprises: removing said silicon-rich oxide residues from said sidewalls by contacting said residues for from about 5 to about 60 seconds with an etchant gas containing at least 40 volume % NF 3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25° C. to about 150° C.

Claim 3

The process of claim 1 wherein at least 50 volume % of said NF 3 -containing etchant gas in said chamber consists of NF 3 .

Claim 4

The process of claim 1 wherein the balance of said etchant gas consists essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF 6 , Cl 2 , and CF 4 .

Claim 5

The process of claim 3 wherein a plasma is maintained in said vacuum chamber during said etch at a power level ranging from about 50 to about 400 watts.

Claim 6

The process of claim 4 wherein said etch is carried out while immersing said wafer in a magnetic field parallel to the plane of the wafer and having a field strength of at least about 25 gauss.

Claim 7

The process of claim 5 wherein said vacuum chamber is maintained at a pressure ranging from about 20 milliTorr to about 1 Torr during said etch.

Claim 8

The process of claim 6 wherein said wafer is maintained at a temperature of from about 5° C. to about 65° C. during said etch.

Claim 9

The process of claim 4 wherein said etch is carried out while immersing said wafer in a magnetic field parallel to the plane of the wafer and having a field strength of from about 25 gauss to about 150 gauss.

Claim 10

The process of claim 5 wherein said vacuum chamber is maintained at a pressure ranging from about 100 milliTorr to about 400 milliTorr during said etch.

Claim 11

The process of claim 5 wherein said vacuum chamber is maintained at a pressure ranging from about 300 milliTorr to about 350 milliTorr during said etch.

Claim 12

The process of claim 6 wherein said wafer is maintained at a temperature of from about 15° C. to about 25° C. during said etch.

Claim 13

The process of claim 6 wherein said NF 3 -containing gas is flowed into said chamber at a rate equivalent to from about 10 to about 500 sccm flowing into a 1200 cc. chamber.

Claim 14

The process of claim 6 wherein said NF 3 -containing gas is flowed into said chamber at a rate equivalent to from about 150 to about 200 sccm flowing into a 1200 cc. chamber.

Claim 15

The process of claim 1 wherein the balance of said etchant gas consists essentially of one or more carrier gases selected from the group consisting of argon, helium, and oxygen.

Claim 16

The process of claim 1 wherein the balance of said etchant gas consists essentially of one or more reactive gases selected from the group consisting of SF 6 , Cl 2 , and CF 4 .

Claim 17

In a process for forming polysilicon lines on an oxide layer formed over underlying steps on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer and wherein polysilicon stringers remain on said oxide layer between adjacent polysilicon lines formed from said polysilicon layer at a position where said oxide layer passes over said underlying steps after said etching step to form said polysilicon lines, the improvement which comprises: removing said polysilicon stringers on said oxide layer by contacting said stringers for from about 5 to about 120 seconds with an etchant gas containing at least 40 volume % NF 3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25° C. to about 150° C.

Claim 18

In a process for forming polysilicon lines on an oxide layer formed over underlying steps on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer and wherein polysilicon stringers remain on said oxide layer between adjacent polysilicon lines formed from said polysilicon layer at a position where said oxide layer passes over said underlying steps after said etching step to form said polysilicon lines, the improvement which comprises: removing said polysilicon stringers on said oxide layer by contacting said stringers for from about 5 to about 120 seconds with an etchant gas containing at least 40 volume % NF 3 in an etchant chamber while maintaining said semiconductor wafer in said etchant chamber within a temperature range of from about -25° C. to about 150° C.

Claim 19

An improvement in the process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement comprising removing said silicon-rich oxide residues from said sidewalls by the steps of: (a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about -5° C. to about 150° C. in a vacuum etch chamber maintained at a pressure within a range of from about 20 milliTorr to about 1 Torr; b) flowing into said etch chamber at a rate equivalent to from about 10 to about 500 sccm flowing into a 1200 cc. vacuum chamber, an NF 3 -containing etchant gas containing at least 40 volume % NF 3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF 6 , Cl 2 , and CF 4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF 3 -containing etchant gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of at least about 25 gauss during said etch; and e) etching said sidewalls of said polysilicon lines for a period of from about 5 to about 60 seconds to remove said silicon-rich oxide residues from said sidewalls of said polysilicon lines.

Claim 20

An improvement in the process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement comprising removing said silicon-rich oxide residues from said sidewalls by the steps of: (a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about -5° C. to about 150° C. in a vacuum etch chamber maintained at a pressure within a range of from about 20 milliTorr to about 1 Torr; b) flowing into said etch chamber at a rate equivalent to from about 10 to about 500 sccm flowing into a 1200 cc. vacuum chamber, an NF 3 -containing etchant gas containing at least 40 volume % NF 3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF 6 , Cl 2 , and CF 4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF 3 -containing etchant gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of at least about 25 gauss during said etch; and e) etching said sidewalls of said polysilicon lines for a period of from about 5 to about 60 seconds to remove said silicon-rich oxide residues from said sidewalls of said polysilicon lines.

Claim 21

The process of claim 17 wherein said pressure is maintained in said vacuum chamber during said etch at a level ranging from about 100 milliTorr to about 400 milliTorr.

Claim 22

The process of claim 17 wherein said magnetic field has a field strength ranging from about 25 gauss to about 150 gauss.

Claim 23

The process of claim 17 wherein said wafer is maintained at a temperature of from about 5° C. to about 65° C. during said etch.

Claim 24

The process of claim 17 wherein said NF 3 -containing gas is flowed into said chamber at a rate equivalent to from about 150 to about 200 sccm flowing into a 1200 cc. chamber.

Claim 25

An improvement in the process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned into raised polysilicon lines on said integrated circuit structure by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement comprising removing said silicon-rich oxide residues from said sidewalls by the steps of: a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about 5° C. to about 65° C. in a vacuum chamber maintained at a pressure within a range of from about 100 milliTorr to about 400 milliTorr; b) flowing into said chamber at a rate equivalent to from about 150 to about 200 sccm flowing into a 1200 cc. vacuum chamber, an NF 3 -containing etchant gas containing at least 50 volume % NF 3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF 6 , Cl 2 , and CF 4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF 3 gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of from about 25 gauss to about 150 gauss during said etch; and e) maintaining said etch conditions for a time period of from about 5 to about 60 seconds; to thereby remove said silicon-rich oxide residues from said sidewalls of said polysilicon lines.

Claim 26

An improvement in the process for forming polysilicon lines over an oxide layer on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned into raised polysilicon lines on said integrated circuit structure by etching through said polysilicon layer down to said underlying oxide layer whereby silicon-rich oxide residues from said etching step are deposited on the sidewalls of said polysilicon lines, the improvement comprising removing said silicon-rich oxide residues from said sidewalls by the steps of: a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about 5° C. to about 65° C. in a vacuum chamber maintained at a pressure within a range of from about 100 milliTorr to about 400 milliTorr; b) flowing into said chamber at a rate equivalent to from about 150 to about 200 sccm flowing into a 1200 cc. vacuum chamber, an NF 3 -containing etchant gas containing at least 50 volume % NF 3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF 6 , Cl 2 , and CF 4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF 3 gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of from about 25 gauss to about 150 gauss during said etch; and e) maintaining said etch conditions for a time period of from about 5 to about 60 seconds; to thereby remove said silicon-rich oxide residues from said sidewalls of said polysilicon lines.

Claim 27

In a process for forming overlying polysilicon lines on an oxide layer formed over underlying polysilicon lines on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer and wherein polysilicon stringers remain on said oxide layer between adjacent overlying polysilicon lines formed from said polysilicon layer at a position where said oxide layer passes over said underlying polysilicon lines after said etching step to form said overlying polysilicon lines, the improvement which comprises: a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about 5° C. to about 65° C. in a vacuum chamber maintained at a pressure within a range of from about 100 milliTorr to about 400 milliTorr; b) flowing into said chamber at a rate equivalent to from about 10 to about 500 sccm flowing into a 1200 cc. vacuum chamber, an NF 3 -containing etchant gas containing at least 50 volume % NF 3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF 6 , Cl 2 , and CF 4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF 3 gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of from about 25 gauss to about 150 gauss during said etch; and e) maintaining said etch conditions for a time period of from about 5 to about 120 seconds.

Claim 28

In a process for forming overlying polysilicon lines on an oxide layer formed over underlying polysilicon lines on an integrated circuit structure formed on a semiconductor wafer wherein a polysilicon layer on said oxide layer is patterned by etching through said polysilicon layer down to said underlying oxide layer and wherein polysilicon stringers remain on said oxide layer between adjacent overlying polysilicon lines formed from said polysilicon layer at a position where said oxide layer passes over said underlying polysilicon lines after said etching step to form said overlying polysilicon lines, the improvement which comprises: a) mounting said wafer on a cathode capable of maintaining a wafer temperature of from about 5° C. to about 65° C. in a vacuum chamber maintained at a pressure within a range of from about 100 milliTorr to about 400 milliTorr; b) flowing into said chamber at a rate equivalent to from about 10 to about 500 sccm flowing into a 1200 cc. vacuum chamber, an NF 3 -containing etchant gas containing at least 50 volume % NF 3 with the balance consisting essentially of one or more gases selected from the group consisting of argon, helium, oxygen, SF 6 , Cl 2 , and CF 4 ; c) igniting a plasma in said chamber and maintaining it at a power level ranging from about 50 to about 400 watts while said NF 3 gas is flowing into said chamber; d) immersing said wafer in said chamber in a magnetic field parallel to the plane of said wafer at a field strength of from about 25 gauss to about 150 gauss during said etch; and e) maintaining said etch conditions for a time period of from about 5 to about 120 seconds.