Register circuit in which a stop current may be measured

Claim 1

A register circuit, comprising: a parallel circuit of N and P channel type transistors connected between an input terminal and a first predetermined node, gates of said N and P channel type transistors being coupled to receive clock pulse and inverted clock pulse signals respectively; a feedback loop circuit of a transmission invertor and a feedback invertor connected between said first predetermined node and a second predetermined node; an output invertor connected between said second predetermined node and an output terminal; a first gate circuit coupled to receive a clock-stop signal and a register circuit-set signal to generate a first gate signal; a second gate circuit to receive said clock-stop signal and a register circuit-reset signal to generate a second gate signal; and a circuit for setting an output of said register circuit to a set state in responses to said first gate signal, and for resetting said output of said register circuit to a reset state in response said second gate signal.