Solid-state long-period timer

Claim 2

A solid-state timer comprising: a retriggerable one-shot having an input lead and an output lead; a timing circuit, said timing circuit being connected to said one-shot; a master-slave flip-flop having first, second, third and fourth input leads and an output lead; first and second reference potentials, said first potential being coupled to said first input lead of said flip-flop, said second input lead of said flip-flop being connected to said output lead of said one-shot, said third input lead of said flip-flop being connected to said second potential; and first and second signal-input terminals, said first input terminal being connected to said input lead of said one-shot, said second input terminal being connected to said fourth input lead of said flip-flop.

Claim 3

A timer as defined in claim 1 wherein said timing circuit includes: a transistor having a base, a collector and an emitter, said emitter of said transistor being connected to said one-shot; first and second resistors, said first resistor being connected between said first potential and said base of said transistor, said second resistor being connected between said first potential and said collector of said transistor; and a capacitor, said capacitor being connected between said one-shot and said base of said transistor.

Claim 4

A timer comprising: a retriggerable one-shot having an input lead and an output lead; a timing circuit, said timing circuit being connected to said one-shot; a master-slave flip-flop having first, second, third and fourth input leads and an output lead, said second input of said flip-flop being connected to said output lead of said one-shot; first and second reference potentials, said first potential being coupled to said first input lead of said flip-flop, said third input lead of said flip-flop being connected to said second potential; a signal-input terminal, said input terminal being connected to said input lead of said one-shot and to said fourth input lead of said flip-flop; a relay having a coil and first and second contacts, said coil of said relay being connected between said second potential and said output lead of said flip-flop; and first and second output terminals, said first output terminal being connected to said first contact of said relay, said second output terminal being connected to said second contact of said relay.

Claim 5

A timer comprising: a retriggerable one-shot having an input lead and an output lead; a timing circuit, said timing circuit being connected to said one-shot; a master-slave flip-flop having first, second, third and fourth input leads and an output lead, said second input of said flip-flop being connected to said output lead of said one-shot; first and second reference potentials, said first potential being coupled to said first input lead of said flip-flop, said third input lead of said flip-flop being connected to said second potential; a signal-input terminal, said input terminal being connected to said input lead of said one-shot and to said fourth input lead of said flip-flop; a relay having a coil and first and second contacts, said coil of said relay being connected between said second potential and said output lead of said flip-flop; and first and second output terminals, said first output terminal being connected to said first contact of said relay, said second output terminal being connected to said second contact of said relay.

Claim 6

A timer as defined in claim 3 wherein said timing circuit includes: a transistor having a base, a collector and an emitter, said emitter of said transistor being connected to said one-shot; first and second resistors, said first reSistor being connected between said first potential and said base of said transistor, said second resistor being connected between said first potential and said collector of said transistor; and a capacitor, said capacitor being connected between said one-shot and said base of said transistor.

Claim 7

A timer comprising: a first retriggerable one-shot having an input lead and and output lead; a first timing circuit, said first timing circuit being connected to said first one-shot; first and second master-slave flip-flops each having first, second, third and fourth input leads and an output lead, said second input lead of said first flip-flop being connected to said output lead of said one-shot; first and second reference potentials, said first potential being coupled to said first input lead of said first flip-flop, said second potential being connected to said third input lead of said first flip-flop, said first input lead of said second flip-flop being connected to said output lead of said first flip-flop, said third input lead of said second flip-flop being connected to said second potential; a signal-input terminal, said input terminal being connected to said input lead of said one-shot and to said fourth input lead of said first flip-flop, said second input lead of said second flip-flop being connected to said input terminal; and means for coupling said input terminal to said fourth input lead of said second flip-flop.

Claim 8

A timer comprising: a first retriggerable one-shot having an input lead and and output lead; a first timing circuit, said first timing circuit being connected to said first one-shot; first and second master-slave flip-flops each having first, second, third and fourth input leads and an output lead, said second input lead of said first flip-flop being connected to said output lead of said one-shot; first and second reference potentials, said first potential being coupled to said first input lead of said first flip-flop, said second potential being connected to said third input lead of said first flip-flop, said first input lead of said second flip-flop being connected to said output lead of said first flip-flop, said third input lead of said second flip-flop being connected to said second potential; a signal-input terminal, said input terminal being connected to said input lead of said one-shot and to said fourth input lead of said first flip-flop, said second input lead of said second flip-flop being connected to said input terminal; and means for coupling said input terminal to said fourth input lead of said second flip-flop.

Claim 9

A timer as defined in claim 5 including: a second retriggerable one-shot having an input lead and an output lead, said input lead of said second one-shot being connected to said output lead of said second flip-flop; a second timing circuit, said second timing circuit being connected to said second one-shot; and an output terminal, said output terminal being connected to said output lead of said second one-shot.

Claim 10

A timer comprising: first and second retriggerable one-shots each having an input lead and an output lead; first and second timing circuits, said first timing circuit being connected to said first one-shot, said second timing circuit being connected to said second one-shot; first and second master-slave flip-flops each having first, second, third and fourth input leads and first and second output leads, said second input lead of said first flip-flop being connected to said output lead of said first one-shot, said second input lead of said second flip-flop being connected to said output lead of said second one-shot; first and second reference potentials, said first potential being coupled to said first input leads of said first and said second flip-flops, said second potential being connected to said third input leads of said first and said second flip-flops; a signal-input terminal, said input terminal being connected to said input leads of said first and said second one-shots, and to said fourth input leads of said first and said second flip-flops; a third master-slave flip-flop having first, second, third, fourth, fifth and sixth input leads and an output lead, said first input lead of said third flip-flop being connected to said first output lead of said first flip-flop, said second input lead of said third flip-flop being connected to said input terminal, said second potential being connected to said third and said sixth input leads of said third flip-flop, said fifth input lead of said third flip-flop being connected to said second output lead of said second flip-flop; and means for coupling said input terminal to said fourth input lead of said third flip-flop.

Claim 11

A timer comprising: first and second retriggerable one-shots each having an input lead and an output lead; first and second timing circuits, said first timing circuit being connected to said first one-shot, said second timing circuit being connected to said second one-shot; first and second master-slave flip-flops each having first, second, third and fourth input leads and first and second output leads, said second input lead of said first flip-flop being connected to said output lead of said first one-shot, said second input lead of said second flip-flop being connected to said output lead of said second one-shot; first and second reference potentials, said first potential being coupled to said first input leads of said first and said second flip-flops, said second potential being connected to said third input leads of said first and said second flip-flops; a signal-input terminal, said input terminal being connected to said input leads of said first and said second one-shots, and to said fourth input leads of said first and said second flip-flops; a third master-slave flip-flop having first, second, third, fourth, fifth and sixth input leads and an output lead, said first input lead of said third flip-flop being connected to said first output lead of said first flip-flop, said second input lead of said third flip-flop being connected to said input terminal, said second potential being connected to said third and said sixth input leads of said third flip-flop, said fifth input lead of said third flip-flop being connected to said second output lead of said second flip-flop; and means for coupling said input terminal to said fourth input lead of said third flip-flop.

Claim 12

A timer as defined in claim 7 including: a third retriggerable one-shot having an input lead and an output lead, said input lead of said third one-shot being connected to said output lead of said third flip-flop; a third timing circuit, said third timing circuit being connected to said third one-shot; and an output terminal, said output terminal being connected to said outPut lead of said third one-shot.

Claim 13

A timer as defined in claim 7 wherein said means for coupling includes: a fourth retriggerable one-shot having an input lead and an output lead, and first and second output leads, said input lead of said fourth one-shot being connected to said input terminal; a fourth timing circuit, said fourth timing circuit being connected to said fourth one-shot, said second output lead of said fourth one-shot being connected to said fourth input lead of said third flip-flop.

Claim 14

A timer as defined in claim 7 including: third and fourth retriggerable one-shots, each having an input lead and first and second output leads, said input lead of said third one-shot being connected to said output lead of said third flip-flop, said input lead of said fourth one-shot being connected to said input terminal, said second output lead of said fourth one-shot being connected to said fourth input lead of said third flip-flop; third and fourth timing circuits, said third timing circuit being connected to said third one-shot, said fourth timing circuit being connected to said fourth one-shot; and an output terminal, said output terminal being connected to said first output lead of said third one-shot.