← Back to Patent Explorer
US4849653A Expired / Lapsed US ⏱️ 0.0 years remaining

Semiconductor circuit device for preventing an output of a bistable circuit from becoming unstable

Assignee: Toshiba Corp
•
Filing: 1988-03-08
•
Granted: 1989-07-18
•
Expires: 2008-03-08
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract There is an R-S flip-flop circuit having a threshold voltage of a first value. An input terminal of a Schmitt trigger circuit having a second threshold voltage of a lower value than the first value and a third threshold voltage of a higher value than the first value is connected to an output terminal of the R-S flip-flop circuit.

Inventors

  • 👤 Kimimasa Imai
  • 👤 Hiroshi Shinya

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-29 23:18
CPC Classifications
H; H03; H03K; H03K3/00; H03K3/02; H03K3/26; H03K3/28; H03K3/281; H03K3/286; H03K3/2893; H03K3/01; H03K3/013; H03K3/353; H03K3/356; H03K3/356017; H03K3/3565

Claims Analysis

Total Claims: 6
Claim 1
Independent Claim 116 words
A semiconductor circuit device comprising: a bistable circuit having a threshold voltage of a first value, said bistable circuit providing an output potential responsive to an input signal; and a Schmitt trigger circuit having a second threshold voltage of a lower valve than said first value and a third threshold voltage of a higher valve than said first valve, said Schmitt trigger circuit also having an input terminal operatively coupled to receive the output potential from said bistable circuit, said Schmitt trigger circuit outputting a first logic level when the output potential rises higher than the third threshold voltage and outputting a second logic level when the output potential falls lower than the second threshold voltage.
Claim 2
Dependent Claim 116 words
A semiconductor circuit device comprising: a bistable circuit having a threshold voltage of a first value, said bistable circuit providing an output potential responsive to an input signal; and a Schmitt trigger circuit having a second threshold voltage of a lower valve than said first value and a third threshold voltage of a higher valve than said first valve, said Schmitt trigger circuit also having an input terminal operatively coupled to receive the output potential from said bistable circuit, said Schmitt trigger circuit outputting a first logic level when the output potential rises higher than the third threshold voltage and outputting a second logic level when the output potential falls lower than the second threshold voltage.
Claim 3
Dependent Claim 27 words
A device according to claim 1, wherein said bistable circuit is an R-S flip-flop circuit having a set signal input terminal and a reset signal input terminal.
Claim 4
Dependent Claim 35 words
A device according to claim 2, wherein said flip-flop circuit comprises first and second inverters connected in parallel such that an output of said first inverter is connected to an input of said second inverter.
Claim 5
Dependent Claim 28 words
A device according to claim 2, wherein said flip-flop circuit comprises first and second NOR gates each having an input connected to the set or reset terminals, respectively.
Claim 6
Dependent Claim 28 words
A device according to claim 2, wherein said flip-flop circuit comprises first and second NAND gates each having an input connected to the set and reset terminals, respectively.

References Cited (Backward Citations)

US3953744A Cited
JPS5779726A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-07-17 1993-01-16 1993-07-18 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-07-17 1997-01-16 1997-07-18 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-07-17 2001-01-16 2001-07-18 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag