Two-state memory device

Claim 2

A bi-stable memory device, comprising: a first input for receiving a binary input signal I₁; a second input for receiving another binary input signal I₂, wherein said I₁ signal is normally generated independently of said I₂ signal; and bi-stable logic circuitry means, connected to said first and second inputs to receive said I₁ and I₂ signals therefrom, and in response thereto, said circuitry means being operable to generate from said I₁ and I₂ signals both a first binary output response signal R₁ and a second binary output response signal R₂, wherein said R₁ signal is the binary complement of said R₂ signal for any binary value of said I₁ and I₂ input signals received by said circuitry means.

Claim 3

The device of claim 1, wherein said logic circuitry means includes a NAND R-S flip-flop (20) having first and second inputs (T₁', T₂'), and first and second outputs (R₁,R₂), and a first inhibit logic (40) having an output (42) connected to said first input (T₁') of said flip-flop (20), and having a first logic input (44) connected to said first input of said device, for receiving said I₁ signal, and further having a second logic input (46), connected to said second input of said device, for receiving said I₂ signal, and including an inverter (56) operatively positioned in said first inhibit logic (40) for inverting said I₂ signal, and a second inhibit logic (48) having an output (50) connected to said second input (T₂') of said flip-flop (20), and having a first logic input (52) connected to said second input of said device, for receiving said I₂ signal, and further having a second logic input (54) connected to said first input of said device, for receiving said I₁ signal, and including another inverter (58) operatively positioned in said second inhibit logic (48) for inverting said I₁ signal.

Claim 4

The device of claim 1, wherein said logic circuitry means includes a NOR R-S flip-flop (62) having first and second inputs (T₁',T₂'), and first and second outputs (R₁,R₂), and a first inhibit logic (82) having an output (86) connected to said first input T₁' of said flip-flop (62), and having a first logic input (88) connected to said first input of said device, for receiving said I₁ signal, and further having a second logic input (90) connected to said second input of said device, for receiving said I₂ signal, and including an inverter (98) operatively positioned in said first inhibit logic (82) for inverting said I₂ signal, and a second inhibit logic (84) having an output (92) connected to said second input T₂' of said flip-flop (62), and having a first logic input (94) connected to said second input of said device, for receiving said I₂ signal, and further having a second logic input (96) connected to said first input of said device, for receiving said I₁ signal, and further including an inverter (100) operatively positioned in said inhibit logic (84) for inverting said I₁ signal.