Method of making polysilicon Schottky clamped transistor and vertical fuse devices

Claim 2

A process for fabricating a semiconductor structure on a substrate having a Schottky transistor in a first area and a vertical fuse in a second area, said transistor including a collector region, an emitter contact region, and a base contact region, said base contact region having a surface adjacent said collector contact region, said vertical fuse including a collector region, an emitter contact region, and a base region, said base region being between said emitter contact region and said collector contact region, the process comprising the steps of: forming a first refractory metal over at least a portion of said transistor base contact region and at least a portion of said collector region adjacent said base region, said first refractory metal forming a rectifying contact between a base and said collector of said transistor; forming a barrier metal over selected areas of said first reacted refractory metal layers, excluding said fuse emitter contact regions; and forming a contact metal over said selected areas of said first reacted refractory metal, said contact metal in direct contact with said fuse emitter contact.

Claim 3

The process of claim 1 before the step of reacting a first refractory metal, further including the step of forming a second refractory metal over selected areas to form a second reacted refractory metal layer, said selected areas contacting at least a portion of a transistor base contact region, at least a portion of a transistor collector contact region, said transistor emitter contact region, and said fuse collector contact region.

Claim 4

The process of claim 2 wherein said barrier contacts selected areas on said second refractory metal layers.

Claim 5

The process of claim 2 wherein said contact metal contacts selected areas of said second reacted refractory metal layers.

Claim 6

The process of claim 2, before wherein the step of forming a first refractory metal further comprises the steps of: masking said fuse device with an oxide layer; etching a contact via through said oxide and a polysilicon contact layer to said at least a portion of said collector region; and forming a silicide of said first refractory metal in contact with said base contact region and said collector region.

Claim 7

The process of claim 5 further comprising the step of etching contact vias in said oxide layer for base, emitter and collector contacts.

Claim 8

The process of claim 1 wherein said first refractory metal layer comprises platinum silicide, and said second refractory metal layer comprises titanium silicide.

Claim 9

The process of claim 1 wherein said barrier metal comprises titanium-tungsten.

Claim 10

A process for fabricating a semiconductor structure having a Schottky transistor in a first area and a vertical fuse device in a second area, the process comprising the steps of: providing a semiconductor substrate; implanting a first type of dopants into said substrate to form a collector region for said Schottky transistor and said vertical fuse device; growing an epitaxial layer over said substrate and said collector regions; implanting a second type of dopants into a base region of said epitaxial layer for said Schottky transistor, said transistor base region isolated from a sink region coupling a part of a surface of said epitaxial layer to said transistor collector region; implanting said second type of dopants into a base region of said epitaxial layer for said vertical fuse device, said fuse base region isolated from a sink region coupling a part of a surface of said epitaxial layer to said fuse collector region; providing said first type dopants in a portion of said polycrystalline layer overlying said base regions and second type dopants in said polycrystalline layer overlying emitter and collector regions, while leaving said polycrystalline layer intrinsic over a collector window region; treating said semiconductor structure to promote a migration of said first dopant types across an interface from said polycrystalline layer into said epitaxial layer to an emitter region overlying said transistor and fuse base regions; forming a first refractory metal over selected areas of said polycrystalline layer to form a first reacted refractory metal layer, said selected areas overlying said transistor base region and a portion of said transistor emitter region; forming a second refractory metal silicide in contact with said collector window region and a base contact region, said second refractory metal forming a rectifying contact between said collector and said base; forming a barrier metal over selected areas of said first and second reacted refractory metal layers, except an emitter contact of said fuse; and forming a contact metal over said barrier metal in direct contact with said emitter contact.

Claim 11

A process for fabricating a semiconductor structure having a Schottky transistor in a first area and a vertical fuse device in a second area, the process comprising the steps of: providing a semiconductor substrate; implanting a first type of dopants into said substrate to form a collector region for said Schottky transistor and said vertical fuse device; growing an epitaxial layer over said substrate and said collector regions; implanting a second type of dopants into a base region of said epitaxial layer for said Schottky transistor, said transistor base region isolated from a sink region coupling a part of a surface of said epitaxial layer to said transistor collector region; implanting said second type of dopants into a base region of said epitaxial layer for said vertical fuse device, said fuse base region isolated from a sink region coupling a part of a surface of said epitaxial layer to said fuse collector region; providing said first type dopants in a portion of said polycrystalline layer overlying said base regions and second type dopants in said polycrystalline layer overlying emitter and collector regions, while leaving said polycrystalline layer intrinsic over a collector window region; treating said semiconductor structure to promote a migration of said first dopant types across an interface from said polycrystalline layer into said epitaxial layer to an emitter region overlying said transistor and fuse base regions; forming a first refractory metal over selected areas of said polycrystalline layer to form a first reacted refractory metal layer, said selected areas overlying said transistor base region and a portion of said transistor emitter region; forming a second refractory metal silicide in contact with said collector window region and a base contact region, said second refractory metal forming a rectifying contact between said collector and said base; forming a barrier metal over selected areas of said first and second reacted refractory metal layers, except an emitter contact of said fuse; and forming a contact metal over said barrier metal in direct contact with said emitter contact.

Claim 12

The process of claim 9 wherein said polycrystalline layer comprises silicon, said first reacted refractory metal comprises titanium silicide, and said second reacted refractory metal layer comprises platinum silicide.

Claim 13

The process of claim 9 wherein said barrier metal comprises titanium-tungsten.