Transistor circuit with controlled collector saturation voltage

Claim 2

A transistor circuit comprising: an input terminal for receiving an input signal; an output terminal for leading out an output signal: a first transistor having an emitter, a base, and a collector, said collector of said first transistor being connected to said output terminal, said base and said collector of said first transistor being free from any connections to a Schottky diode; a second transistor having a base and having a collector-emitter passage connected between said input terminal and the collector of said first transistor; a PN junction element connected between said input terminal and the base of said first transistor; a first resistor connected between the collector and base of said second transistor; a second resistor connected between the base and emitter of said second transistor; a load having one end connected to the collector of said first transistor; and means for supplying operating power between said emitter of said first transistor and another end of said load, whereby said first transistor is prevented from being driven into saturation condition without using any Schottky diode.

Claim 3

A transistor circuit as claimed in claim 1 wherein said PN junction element is a base-emitter junction of a third transistor.

Claim 4

A transistor circuit as claimed in claim 2 wherein the ratio between the resistance values of said first resistor and second resistor is "1" or below.

Claim 5

A transistor circuit as claimed in claim 1 wherein said second transistor has a collector connected to said input terminal and an emitter connected to the collector of said first transistor.

Claim 6

A transistor circuit as claimed in claim 2 wherein said load is a fourth transistor having a base connected to a collector of said third transistor, an emitter operating as said one end of said load, and a collector operating as said other end of said load.

Claim 7

A transistor circuit comprising: an input terminal for receiving an input signal; a first transistor having a base connected to said input terminal and having a collector and an emitter, said base and said collector of said first transistor being free from any connections to a Schottky diode; a second transistor having a base connected to the emitter of said first transistor, and having a collector and an emitter, said base and said collector of said second transistor being free from a Schottky diode; a third transistor having a base connected to the collector of said first transistor, and having a collector and an emitter, said base and said collector of said third transistor being free from any connections to a Schottky diode; an output terminal; means for connecting the collector of said second transistor, the emitter of said third transistor, and said output terminal; a fourth transistor having a base and having an emitter-collector path inserted between the base of said first transistor and the collector of said second transistor; a first resistor connected between the collector and base of said fourth transistor; a second resistor connected between the emitter and base of said fourth transistor; and means for supplying power between the collector of said third transistor and the emitter of said second transistor, whereby said second transistor is kept in a non-saturation condition without using any Schottky diode.

Claim 8

A transistor circuit comprising: an input terminal for receiving an input signal; a first transistor having a base connected to said input terminal and having a collector and an emitter, said base and said collector of said first transistor being free from any connections to a Schottky diode; a second transistor having a base connected to the emitter of said first transistor, and having a collector and an emitter, said base and said collector of said second transistor being free from a Schottky diode; a third transistor having a base connected to the collector of said first transistor, and having a collector and an emitter, said base and said collector of said third transistor being free from any connections to a Schottky diode; an output terminal; means for connecting the collector of said second transistor, the emitter of said third transistor, and said output terminal; a fourth transistor having a base and having an emitter-collector path inserted between the base of said first transistor and the collector of said second transistor; a first resistor connected between the collector and base of said fourth transistor; a second resistor connected between the emitter and base of said fourth transistor; and means for supplying power between the collector of said third transistor and the emitter of said second transistor, whereby said second transistor is kept in a non-saturation condition without using any Schottky diode.

Claim 9

A transistor circuit as claimed in claim 6 wherein said connecting means is a diode having one end connected to the emitter of said third transistor and the other end connected to the collector of said second transistor and said output terminal.

Claim 10

A transistor circuit as claimed in claim 6 wherein said first, second, third and fourth transistors have the same conductivity type, and said fourth transistor has a collector connected to the base of said first transistor and an emitter connected to the collector of said second transistor.

Claim 11

A transistor circuit as claimed in claim 6 wherein the resistance ratio of said first resistor to said second resistor is equal to or less than one.