Power efficient TTL buffer for driving large capacitive loads

Claim 2

In a TTL gate comprising a power supply for supplying collector current to said gate, input means for receiving an input signal, output means responsive to said input signal for providing logic high and low level outputs from said gate at an output node, and drive means connected between said input means and said output means for driving said output means with said collector current, the improvement comprising: feedback means, connected between an output of said drive means and said output means, for altering the response of said drive means to substantially reduce said collector current from said power supply when said output node reaches said logic low output level.

Claim 3

A TTL gate as defined in claim 1 wherein said drive means is a first current mirror circuit including a main drive transistor having multi-emitters, the first emitter of said main drive transistor forming part of said first current mirror circuit, the second emitter of said main drive transistor connected to said feedback means whereby activation of said feedback means reduces said collector current supplied to said first current mirror circuit.

Claim 4

A TTL gate as defined in claim 2 wherein said first current mirror circuit is a ratioed current mirror.

Claim 5

A TTL gate as defined in claim 2 wherein said feedback means is a second current mirror circuit having a first leg connected to said second emitter of said main drive transistor and a second leg connected to said output means and said first current mirror circuit.

Claim 6

A TTL gate as defined in claim 4 wherein said second current mirror circuit is a ratioed current mirror.

Claim 7

A TTL gate as defined in claim 1 wherein said drive means includes a main drive transistor having a collector, base and multi-emitters, and a auxiliary drive transistor having a collector, base, and emitter; said collectors of said main and auxiliary drive transistors being connected to said power supply, said bases of said main and auxiliary drive transistors being tied together; a first emitter of said main drive transistor and said emitter of said auxiliary drive transistor being connected to form a first current mirror means.

Claim 8

A TTL gate as defined in claim 6, wherein said first current mirror means is a ratioed current mirror between said emitter of said auxiliary drive transistor and said first emitter of said main drive transistor to provide an increase in the drive current available to drive said output means.

Claim 9

A TTL gate as defined in claim 6 wherein said feedback means includes first and second feedback transistors each having a base, collector, and emitter; said collector of said first feedback transistor connected to a second emitter of said main drive transistor, said bases of said first and second feed-back transistors being connected to said first emitter of said main drive transistor and said emitter of said auxiliary drive transistor, said emitters of said first and second feedback transistors being connected to said output node, said collector of said second feedback transistor connected to said output means; said first and second feedback transistors forming a second current mirror means.

Claim 10

A TTL gate as defined in claim 8, wherein said second current mirror means is a ratioed current mirror.

Claim 11

A TTL gate as defined in claim 2, wherein said input means includes a main input transistor having a base, collector, and multi-emitters, said base of said main input transistor connected to said base of said main drive transistor and said base of said auxiliary drive transistor, said input line forming one of the emitters of said main input transistor.

Claim 12

A TTL gate as defined in claim 10, wherein said input means includes an auxiliary input transistor having a base, collector, and emitter; said base of said auxiliary input transistor connected to said collector of said main input transistor, said collector of said auxiliary input transistor connected to said power supply, said emitter of said auxiliary input transistor connected to said base of said main input transistor; said auxiliary input transistor serving to supply base drive to said main input transistor and said drive means.

Claim 13

A TTL gate as defined in claim 11, including a series diode and resistor combination connected between said base of said auxiliary input transistor and said collector of said main drive transistor for keeping said main drive transistor out of saturation when the output node goes to the logic low level.

Claim 14

A TTL gate as defined in claim 10, wherein the second emitter of said main input transistor is used for tri-state operation of said gate.

Claim 15

A TTL gate as defined in claim 1, including pull-up transistor means connected between said power supply and said output means for providing an active pull-up of said output node for improved gate speed.

Claim 16

A TTL gate as defined in claim 14, wherein said pull-up transistor means is a Darlington amplifier.

Claim 17

A TTL gate as defined in claim 1 including compensation diodes for radiation hardness.

Claim 18

A TTL gate for driving large capacitive loads, comprising: a power supply for supplying collector current to said gate; input means connected to said power supply, said input means having an input line for receiving an input signal; output transistor means responsive to said input signal for providing logic high and low level outputs from said gate at an output node; first current mirror means connected between said input means and said output transistor means for controlling a drive current supplied to said output means in response to said input signal; and feedback means connected between said first current mirror means and said output transistor means for disrupting the operation of said first current mirror means when said logic low output level is reached such that said collector current is reduced.

Claim 19

A TTL gate for driving large capacitive loads, comprising: a power supply for supplying collector current to said gate; input means connected to said power supply, said input means having an input line for receiving an input signal; output transistor means responsive to said input signal for providing logic high and low level outputs from said gate at an output node; first current mirror means connected between said input means and said output transistor means for controlling a drive current supplied to said output means in response to said input signal; and feedback means connected between said first current mirror means and said output transistor means for disrupting the operation of said first current mirror means when said logic low output level is reached such that said collector current is reduced.

Claim 20

A TTL gate for driving large capacitive loads as defined in claim 17, wherein said first current mirror means comprises a main drive transistor having a base, collector, and multi-emitters, and an auxiliary drive transistor having a base, collector, and emitter; said emitter of said auxiliary drive transistor being connected to the first emitter of said main drive transistor to form said first current mirror means; said collectors of said main and auxiliary drive transistors being connected to said power supply; said bases of said main and auxiliary drive transistor tied together.

Claim 21

A TTL gate for driving large capacitive loads as defined in claim 18, wherein said first current mirror means is an n:1 current mirror which provides a n+1:1 increase in said drive current available to drive said output transistor means.

Claim 22

A TTL gate for driving large capacitive loads as defined in claim 18, wherein said feedback means comprises first and second feedback transistors each having a base, collector, and emitter; said collector of said first feedback transistor connected to the second emitter of said main drive transistor, said bases of said first and second feedback transistors being connected to said first emitter of said main drive transistor, said emitters of said first and second feedback transistors being connected to said output node; said collector of said second feedback transistor connected to said output transistor means.

Claim 23

A TTL gate for driving large capacitive loads as defined in claim 20, wherein said feedback means is a n:1 current mirror which provides a n+1:1 decrease in said collector current supplied to said output means.

Claim 24

A TTL gate for driving large capacitive loads as defined in claim 17, wherein said input means includes a means for tri-stating said gate.

Claim 25

A TTL gate for driving large capacitive loads as defined in claim 17, including active pull-up means connected between said power supply and said output transistor means for providing an active pull-up of said output node for improved gate speed.

Claim 26

A TTL gate for driving large capacitive loads as defined in claim 17 including compensation diodes for radiation hardness.