Oxide isolation process for standard RAM/PROM and lateral PNP cell RAM

Claim 2

Semiconductor structure comprising: a substrate of a first conductivity type; an epitaxial layer of a second conductivity type opposite said first conductivity type formed on said substrate; a laterally extending PN isolation junction formed between said epitaxial layer and said substrate; oxidized portions of said epitaxial layer formed through said epitaxial layer to the laterally extending PN isolation junction thereby to form a plurality of islands of semiconductor material from said epitaxial lay p r, selected ones of said islands being isolated from the other islands by said oxidized portions of said epitaxial laver and the laterally extending PN isolation junction; characterized hy comprising : a plurality of transistors formed on a one-to-one basis in a corresponding plurality of said islands of semiconductor material, each transistor having an emitter region of second conductivity type, a base region of first conductivity type and a collector region of second conductivity type wherein PN junctions are formed between said emitter and base regions and between said base and collector regions; first means for contacting said emitter reaion; and second means for contactinq said collector reqion; wherein selected ones of said plurality of transistors have been altered hy having the PN junctions between their base and emitter regions destroyed thereby to form an electrical short circuit between their emitter and base regions.

Claim 3

The structure of Claim 1 characterized in that each of said altered transistors represents a first state of information and those transistors not altered represent a second state of information, such that said structure comprises a programmed read-only memory.

Claim 4

The structure of Claim 1 or 2 characterized in that regions of said transistors are formed in the base regions of said transistors such that only the leading ed q e of each base region protrudes past each emitter region, thereby to yield a shallow base with a high dopant concentration qradient for fast transit times in an NPN transistor.

Claim 5

The structure of Claim 2 characterized in that each emitter-base junction destroyed to form a programmable read-only memory device has its lateral dimensions defined completely by the oxidized portions of said epitaxial layer and wherein the base region also has its lateral dimensions defined completely by the oxidized portions of said epitaxial layer.

Claim 6

The structure of Claim 4 characterized by including an LV CEO implanted region of first conductivity type formed in the base region directly adjacent said oxidized portions of said epitaxial layer from the same impurity type used to from said base region thereby to increase the collector-emitter breakdown voltage of each of said transistors, and a high value resistor formed in said epitaxial layer from said impurity.

Claim 7

Structure as in Claim 1 characterized in that said means for contacting said collector region comprises a buried contact region of the same conductivity type as said epitaxial layer but of higher dopant concentration than said epitaxial layer formed in said substrata directly beneath said epitaxial layer and extending partially into said epitaxial layer, said buried contact region extending underneath an oxidized portion of said epitaxial layer into contact with a second island of semiconductor material formed from said epitaxial layer, said second island of semiconductor material comprising a contact region extending to the top surface of said epitaxial laver, thereby to allow contact to be made to said collector region.

Claim 8

Structure as in Claim 6 characterized in that said second island of semiconductor material includes a top region of the second conductivity type but of a higher impurity concentration than said epitaxial laver.

Claim 9

Structure as in Claim 1 characterized by including a region of higher dopan- concentration than but of the same conductivity type as said base region of first conductivity type formed in said base region directly adjacent the oxidized portions of said epitaxial layer defining the lateral dimensions of said base region thereby to increase the LV CEO of said vertical transistor while lowering the transistor qain.

Claim 10

Structure as in Claim 1 characterized in that said second means for contacting said collector region comprises a multiplicity of islands of semiconductor material defined bv oxidized portions of said epitaxial layer, each of said islands of semiconductor material being connected by a buried contact region formed in said underlying substrate and extending into said epitaxial layer, and extending from said island of semiconductor material to the collector regions of N vertical transistors formed in adjacent islands of semiconductor material defined by oxidized portions of said epitaxial layer, where N is a selected positive integer, thereby to reduce the number of islands of semiconductor material used to contact said collector regions of said plurality of transistors, and thus to increase the packina densitv of said structure.

Claim 11

Structure as in Claim 9 characterized in that N is 4.

Claim 12

Structure as in Claim 9 characterized in that N is 2.

Claim 13

Structure as in Claim 9 characterized by including a selected number of bit lines, each bit line being arranged parallel to the other bit lines and each bit line overlying and making electrical contact to the emitter regions of a selected number of said plurality of vertical transistors; and wherein said structure includes a multiplicity of word lines substantially orthogonal to said bit lines, each of said word lines being insulated from said bit lines and overlying and making electrical contact to a selected number of said second means for contacting said collector reqions; whereby said structure comprises a programmable read-only memory.

Claim 14

Semiconductor structure comprising: a substrate of a first conductivity type; an epitaxial layer of a second conductivity type opposite said first conductivity type formed on said substrate; a laterally extending PN isolation junction formed between said epitaxial layer and said substrate; oxidized portions of said epitaxial layer formed through said epitaxial layer to the laterally extending PN isolation junction thereby to form a plurality of islands of semiconductor material from said epitaxial laver, selected ones of said islands being isolated from the other islands by said oxidized portions of said epitaxial layer and the laterally extendinq PN isolation junction; characterized by a plurality of vertical transistors formed on a one-to-one basis in a corresponding nlur al ity of said islands ofsemiconductor material, each vertical transistor having an emitter reqion of second conductivity tyne, a base region of first conductivity type and a collector region of second conductivity type wherein PN junctions are formed between said emitter and base regions and between said base and collector regions; first means for contactinq said emitter region; second means for contacting said collector region; a second region of first conductivity tvpe formed in each of said islands of semiconductor material laterally displaced from said base region of first conductivity type formed in each of said islands by a portion of said epitaxial layer; said second region forminq the emitter of a lateral transistor, said base region forming the collector of said lateral transistor and that portion of said epitaxial layer separating the emitter region from the collector region of said lateral transistor forming the base reqion of said lateral transistor, and wherein said second means for contacting said collector region also comprises means for contactinq said base region of said lateral transistor.

Claim 15

Semiconductor structure comprising: a substrate of a first conductivity type; an epitaxial layer of a second conductivity type opposite said first conductivity type formed on said substrate; a laterally extending PN isolation junction formed between said epitaxial layer and said substrate; oxidized portions of said epitaxial layer formed through said epitaxial layer to the laterally extending PN isolation junction thereby to form a plurality of islands of semiconductor material from said epitaxial laver, selected ones of said islands being isolated from the other islands by said oxidized portions of said epitaxial layer and the laterally extendinq PN isolation junction; characterized by a plurality of vertical transistors formed on a one-to-one basis in a corresponding nlur al ity of said islands ofsemiconductor material, each vertical transistor having an emitter reqion of second conductivity tyne, a base region of first conductivity type and a collector region of second conductivity type wherein PN junctions are formed between said emitter and base regions and between said base and collector regions; first means for contactinq said emitter region; second means for contacting said collector region; a second region of first conductivity tvpe formed in each of said islands of semiconductor material laterally displaced from said base region of first conductivity type formed in each of said islands by a portion of said epitaxial layer; said second region forminq the emitter of a lateral transistor, said base region forming the collector of said lateral transistor and that portion of said epitaxial layer separating the emitter region from the collector region of said lateral transistor forming the base reqion of said lateral transistor, and wherein said second means for contacting said collector region also comprises means for contactinq said base region of said lateral transistor.

Claim 16

Structure as in Claim 13 characterized in that at least three of the four sides of the emitter region and collector region of the lateral transistor and two of the four sides of the collector region of the vertical transistor have their lateral dimensions defined by oxidized portions of said epitaxial layer.

Claim 17

Structure as in Claim 13 characterized in that each of said lateral transistors serve as a load in a circuit to be formed including the vertical transistor formed in the same island of semiconductor material.

Claim 18

Structure as in Claim 14 characterized in that the betas of said lateral transistors are in the ranae of 0.2 - 2.0.

Claim 19

Structure as in Claim 14 characterized by includina channel stop reqions of the same impurity type as, but of a higher dopant concentration than, said substrate formed in said structure directly beneath portions of said oxidized portions of said epitaxial layer and further including third regions of second conductivity type but of a higher dopant concentration than said epitaxial layer formed in said epitaxial layer directly adjacent said oxidized portions of said epitaxial layer from the oile-up of impurities qenerated by the thermal oxidation of said epitaxial layer thereby to provide vertical isolation between the base region of the vertical transistor and the channel stop regions under the field oxide.

Claim 20

Method of forming a semiconductor device comprising: forminq in a semiconductor substrate of a first conductivity type a first pluralitv of first regions of a second conductivity type adjacent the top surface thereof, said second conductivity type beinq opposite said first conductivitv type, said first region of said second conductivity tvpe being highly doped to provide a low resistivity to the passage of current; forming an epitaxial layer of said second conductivity type on said substrate to a selected thickness, said first regions out-diffusing from said substrate into portions of said epitaxial laver during the qrowth of said epitaxial layer; characterized by further comprising the steps of: forming grooves in selected pcrtions of said epitaxial layer, said grooves overlying at least those portions cf said substrate not occupied by said first regions; forming channel stop regions of said first conductivity type in the bottom surfaces of said grooves, said channel stop regions of first conductivity type having a higher dopant concentration than said substrate; thermally oxidizing the epitaxial silicon material exposed by said grooves, thereby to form regions of thermal oxide in said grooves, said regions of thermal oxide extending through said epitaxial layer into contact with said first regionsthereby to form a second plurality of islands of semiconductor material from said epitaxial layer, the lateral dimensions of each of said islands being defined by said regions of thermal cxide; forming second and third regions in each of a selected number of said islands of semiconductor material, said second and third regions being of first conductivity type and being laterally separated from each other by a portion of said epitaxial layer, the lateral dimensions of said second and third regions being determined on all but one side by said thermal oxide; etching portions of the regions of thermal oxide adjacent said third regions so as to expose additional portions of each of said selected number of said islands of semiconductor material; forming in each of said third regions a fourth region and a fifth region of said second conductivity type, said fourth region and said fifth region being separated laterally from each other by a portion of said third region, said fifth region being formed at least in part in said exposed additional portion of said island of semiconductor material to abut directly a portion of the reqion of thermal oxide formed in the groove adjacent the island of semiconductor material in which said fifth reqion is formed; forming in each of said third regions a higher impurity concentration of the dopant of said first conductivity type directly beneath said fourth and fifth regions, therebv to reduce leakage between said fourth region and said epitaxial layer, and between said fifth region and said epitaxial 1ayer; forming electrical contacts to said second region, said third region, said fourth region and said fifth region; and forming an electrical contact to said first region, thereby to form a contact to said epitaxial layer, said epitaxial layer functioning as the collector of a transistor comprising said epitaxial layer, said third region as a base and said fourth and fifth regions as multiple emitters, and said epitaxial layer further functioning as the base of a lateral transistor comprising said second reqion as an emitter, and said third region as a collector.

Claim 21

Method of forming a semiconductor device comprising: forminq in a semiconductor substrate of a first conductivity type a first pluralitv of first regions of a second conductivity type adjacent the top surface thereof, said second conductivity type beinq opposite said first conductivitv type, said first region of said second conductivity tvpe being highly doped to provide a low resistivity to the passage of current; forming an epitaxial layer of said second conductivity type on said substrate to a selected thickness, said first regions out-diffusing from said substrate into portions of said epitaxial laver during the qrowth of said epitaxial layer; characterized by further comprising the steps of: forming grooves in selected pcrtions of said epitaxial layer, said grooves overlying at least those portions cf said substrate not occupied by said first regions; forming channel stop regions of said first conductivity type in the bottom surfaces of said grooves, said channel stop regions of first conductivity type having a higher dopant concentration than said substrate; thermally oxidizing the epitaxial silicon material exposed by said grooves, thereby to form regions of thermal oxide in said grooves, said regions of thermal oxide extending through said epitaxial layer into contact with said first regionsthereby to form a second plurality of islands of semiconductor material from said epitaxial layer, the lateral dimensions of each of said islands being defined by said regions of thermal cxide; forming second and third regions in each of a selected number of said islands of semiconductor material, said second and third regions being of first conductivity type and being laterally separated from each other by a portion of said epitaxial layer, the lateral dimensions of said second and third regions being determined on all but one side by said thermal oxide; etching portions of the regions of thermal oxide adjacent said third regions so as to expose additional portions of each of said selected number of said islands of semiconductor material; forming in each of said third regions a fourth region and a fifth region of said second conductivity type, said fourth region and said fifth region being separated laterally from each other by a portion of said third region, said fifth region being formed at least in part in said exposed additional portion of said island of semiconductor material to abut directly a portion of the reqion of thermal oxide formed in the groove adjacent the island of semiconductor material in which said fifth reqion is formed; forming in each of said third regions a higher impurity concentration of the dopant of said first conductivity type directly beneath said fourth and fifth regions, therebv to reduce leakage between said fourth region and said epitaxial layer, and between said fifth region and said epitaxial 1ayer; forming electrical contacts to said second region, said third region, said fourth region and said fifth region; and forming an electrical contact to said first region, thereby to form a contact to said epitaxial layer, said epitaxial layer functioning as the collector of a transistor comprising said epitaxial layer, said third region as a base and said fourth and fifth regions as multiple emitters, and said epitaxial layer further functioning as the base of a lateral transistor comprising said second reqion as an emitter, and said third region as a collector.

Claim 22

The method of Claim 18 characterized in that the step of forming said second re q ion and said third region comprises forming a pattern of photoresist material over the surface of selected ones of said second nlurality of islands of semiconductor material sufficiently thick to block the implantation of ions over those reaions where ions of the first conductivity type are not to be implanted into said silicon island; and implanting an impurity of said first conductivity type into said islands therebv to form said second and third reqions.

Claim 23

The method of claim 18 characterized in that the step of forminq said fourth and fifth r p qions comprises forming a masking material over all portions of the surface of said silicon islands exceot those portions beneath which said fourth and fifth reqions are to be formed; and implanting a selected impurity of said second conductivity type into said silicon islands in those regions not blocked by said masking material, thereby to form said fourth and fifth reqions.

Claim 24

The method of Claim 19 characterized in that said second and third regions are implanted into said silicon islands by implanting B+ ions at a dose of about 7.0x10 13 /cm 2 and at an energy of 117 KEV.

Claim 25

The method as in Claim 20 characterized in that said fourth and fifth reqions are formed by usina As ions at a dose of about 1x10 16 /cm 2 and an energy of about 60 KEV, implanting arsenic thereby to form an emitter-base junction.

Claim 26

The method as in Claim 22 characterized in that said structure is thermally annealed to drive said emitter-base junction to a depth of about 0.3 microns beneath the top surface of the epitaxial layer and to yield a peak concentration of about 2x10 20 atoms/cm3.

Claim 27

The method of Claim 19 characterized in that a P type dopant is formed in said third region beneath said fourth and fifth regions by implanting boron at a density of 6.4x10 12 /cm 2 and at an energy of 150 KEV.

Claim 28

The method of Claim 18 characterized in that the step of forming said grooves overlvinq portions of said substrate not occupied by said first regions comprises: forming a layer of silicon dioxide on said epitaxial layer; forming a layer of silicon nitride on said silicon dioxide; removing those portions of silicon nitride and silicon dioxide overlying the portions of said epitaxial layer to be removed to form said grooves, said process of removing said silicon dioxide layer including the process of etching away portions of said silicon dioxide layer beneath the lateral extremities of said silicon nitride layer so as to leave extensions of said silicon nitride overhanging said silicon dioxide; and removing nortions of said epitaxial layer exposed by removal of said silicon dioxide and silicon nitride thereby to form said grooves and to leave said second plurality of islands of semiconductor material, said silicon being removed laterally beneath the overhangs of said silicon nitride thereby to form sidewalls on said silicon islands recessed underneath the overhangs of said silicon nitride layer.

Claim 29

The method as in Claim 25 characterized in that said step of forming said channel stop regions of said first conductivity type comprises: forming said channel stop regions of first conductivity type in the bottoms of said grooves laterally displaced from said silicon islands in an amount determined hy the amount of overhan q of said silicon nitride over said silicon semiconductor islands, thereby to prevent said channel stop regions of said first conductivity type form laterallv diffusing to said silicon islands durinq subsequent processinq of said wafer.

Claim 30

Method of forming a semiconductor device comprising: forming in a silicon semiconductor substrate of a first conductivity type a first plurality of first regions adjacent the top surface thereof of a second conductivity type, said second conductivity type beinq opposite said first conductivity type, said first reqions of said second conductivity type beinq highly doped to provide a low resistivity to the passage of current; forming a silicon eoitaxial layer of said second conductivity type on said substrate to a selected thickness, said first reqions out-diffusing from said substrate into portions of said epitaxial layer during the growth of said epitaxial layer; characterized by further comprising the steps of: forming grooves in selected portions of said epitaxial layer, said grooves overlying those portions of said substrate not occupied by said first regions; forming channel stop reqions of said first conductivity type in the bottom surfaces of said grooves, said channel stop regions of said first conductivity tvpe having a higher donant concentration than said substrate; thermally oxidizing the epitaxial silicon material exposed by said grooves, thereby to form regions of thermal oxide in said grooves, said reqions of thermal oxide extending through said epitaxial layer into contact with said first regions formed in said substrate and the lower portion of said epitaxial layer, thereby to form a second plurality of islands of semiconductor material from said epitaxial laver, the lateral dimensions of each of said islands being defined hv said regions of thermal oxide; forming a second region of first conductivity type in each of selected ones of said islands of semiconductor material, each of said second regions having its lateral extent defined bv said thermal oxide on all sides of the island of semiconductor material in which said second region is formed; and forming a third region of second conductivity type above said second region in said selected ones of said islands of semiconductor material, thereby to form a vertical transistor in each of said selected islands, said epitaxial layer forming the collector of said vertical transistor, said second region forming the base of said vertical transistor, and said third region forming the emitter of said vertical transistor.

Claim 31

Method of forming a semiconductor device comprising: forming in a silicon semiconductor substrate of a first conductivity type a first plurality of first regions adjacent the top surface thereof of a second conductivity type, said second conductivity type beinq opposite said first conductivity type, said first reqions of said second conductivity type beinq highly doped to provide a low resistivity to the passage of current; forming a silicon eoitaxial layer of said second conductivity type on said substrate to a selected thickness, said first reqions out-diffusing from said substrate into portions of said epitaxial layer during the growth of said epitaxial layer; characterized by further comprising the steps of: forming grooves in selected portions of said epitaxial layer, said grooves overlying those portions of said substrate not occupied by said first regions; forming channel stop reqions of said first conductivity type in the bottom surfaces of said grooves, said channel stop regions of said first conductivity tvpe having a higher donant concentration than said substrate; thermally oxidizing the epitaxial silicon material exposed by said grooves, thereby to form regions of thermal oxide in said grooves, said reqions of thermal oxide extending through said epitaxial layer into contact with said first regions formed in said substrate and the lower portion of said epitaxial layer, thereby to form a second plurality of islands of semiconductor material from said epitaxial laver, the lateral dimensions of each of said islands being defined hv said regions of thermal oxide; forming a second region of first conductivity type in each of selected ones of said islands of semiconductor material, each of said second regions having its lateral extent defined bv said thermal oxide on all sides of the island of semiconductor material in which said second region is formed; and forming a third region of second conductivity type above said second region in said selected ones of said islands of semiconductor material, thereby to form a vertical transistor in each of said selected islands, said epitaxial layer forming the collector of said vertical transistor, said second region forming the base of said vertical transistor, and said third region forming the emitter of said vertical transistor.

Claim 32

The method of Claim 27 characterized by including the steps of: forming an electrical contact to each of said collector regions by forming an adjacent island of semiconductor material overlying the first region beneath said collector region but separated laterally thereform by a portion of said regions of thermal oxide, and forming in said adjacent island of semiconductor material a fourth region of said second conductivity type but of higher concentration than the dopant in said epitaxial layer, said fourth region extending through said epitaxial layer to said first region of second conductivity type, said first region of second conductivitv type extending underneath a portion of said thermal oxide into contact with said collector region of said vertical transistor thereby to provide an electrical connection between said fourth reqion and said collector region. 29. The method of Claim 18 or 27 characterized in that the number of islands of semiconductor material exceeds the number of first regions of a second conductivity type and wherein portions of said regions of thermal oxide extend over portions of said first regions thereby to laterally separate N islands of semiconductor material formed over the same first region such that said N islands are electrically connected by said first region, where N is a selected positive integer.