US4851715A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Schottky-clamped transistor logic buffer circuit
Assignee: Texas Instruments Inc
•
Filing: 1988-12-20
•
Granted: 1989-07-25
•
Expires: 2008-12-20
Abstract
Abstract A high speed interstage STL buffer (27) is disclosed having a low threshold and high driving capability. A first Schottky-clamped grounded emitter transistor (28) receives input signals through a Schottky steering diode (38) and inverts the input signal. The input signal is applied in parallel through a Schottky steering diode (20) to a second Schottky-clamped grounded emitter transistor (12). The collector (22) of the second transistor (12) provides an output of the buffer (27) for driving load current in one direction with respect to the buffer output. A third transistor (40) connected as an emitter follower has the emitter (42) thereof connected to the buffer output for driving load currents in the other direction. The base (46) of the emitter follower transistor (40) is coupled by a Schottky steering diode (50) to the collector (32) of the first transistor (28). The steering diodes (20, 38, 50) have a forward threshold voltage less than that of the Schottky-barrier diodes used to clamp the base-collector junctions of the first and second transistors (28, 12).
Inventors
- 👤 Bob D. Strong
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-05 23:46
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/08; H03K19/082; H03K19/084; H03K19/0846
Claims Analysis
Total Claims: 13
Claim 1
Independent Claim
177 words
A high speed logic buffer circuit, comprising: an input for receiving signals thereon for driving the buffer circuit; an output for driving other electrical apparatus; a first transistor having a Schottky-clamped base and collector junction and having an emitter, said base being driven by signals on said input, and said collector being connected to a potential for allowing collector and emitter current to flow, with its emitter directly connected to ground; a second transistor having a Schottky-clamped base and collector junction, and having an emitter connected to ground allowing collector and emitter current flow, the collector of said second transistor being connected to said output for allowing current flow in a first direction with respect to said output, the base of said second transistor receiving said input signals; and a third transistor having a base driven by signals on the collector of said first transistor, an emitter connected to said output and a ollector connected to a potential for allowing current to flow in a second direction opposite to said first direction with respect to said output.
Claim 2
Dependent Claim
177 words
A high speed logic buffer circuit, comprising: an input for receiving signals thereon for driving the buffer circuit; an output for driving other electrical apparatus; a first transistor having a Schottky-clamped base and collector junction and having an emitter, said base being driven by signals on said input, and said collector being connected to a potential for allowing collector and emitter current to flow, with its emitter directly connected to ground; a second transistor having a Schottky-clamped base and collector junction, and having an emitter connected to ground allowing collector and emitter current flow, the collector of said second transistor being connected to said output for allowing current flow in a first direction with respect to said output, the base of said second transistor receiving said input signals; and a third transistor having a base driven by signals on the collector of said first transistor, an emitter connected to said output and a ollector connected to a potential for allowing current to flow in a second direction opposite to said first direction with respect to said output.
Claim 3
Dependent Claim
23 words
The buffer circuit of claim 1 further including a first Schottky diode connected between said input and the base of said first transistor.
Claim 4
Dependent Claim
23 words
The buffer circuit of claim 2 further including a second Schottky diode connected between said input and the base of said second transistor.
Claim 5
Dependent Claim
38 words
The buffer circuit of claim 3 wherein the forward threshold voltage of each said first and second diodes is less than the forward threshold voltage of the base and collector junctions of the respective first and second transistors.
Claim 6
Dependent Claim
23 words
The buffer circuit of claim 1 wherein the collector of said second transistor is connected directly to the emitter of said third transistor.
Claim 7
Dependent Claim
26 words
The buffer circuit of claim 1 further including a Schottky diode connected between the collector of said first transistor and the base of said third transistor.
Claim 8
Dependent Claim
21 words
The buffer of claim 1 further including means for operating said buffer circuit between a ground potential and about 2 volts.
Claim 9
Dependent Claim
213 words
A Schottky transistor buffer circuit, comprising: a first input for receiving input driving signals; an output for supplying bidirectional currents to a load; a first bipolar transistor having a Schottky-clamped base-collector junction and an emitter directly connected to ground, and further including a first Schottky diode with an anode connected to the base of said first transistor and a cathode connected to said input, and a bias resistor connected between a source of voltage and the base of said first transistor; a second bipolar transistor having a Schottky-clamped base-collector junction, a grounded emitter, and including a second Schottky diode with an anode connected to the base of said second transistor and a cathode connected to said input, and further including a resistor connected between a source of voltage and the base of said second transistor, the collector of said second transistor being connected to said output; and a third transistor having a collector connected to a source of voltage, an emitter connected to said output, a base, and including a third Schottky diode with an anode connected to the base of said third transistor and a cathode connected to the collector of said first transistor, and further including a resistor connected between a source of voltage and the base of said third transistor.
Claim 10
Dependent Claim
213 words
A Schottky transistor buffer circuit, comprising: a first input for receiving input driving signals; an output for supplying bidirectional currents to a load; a first bipolar transistor having a Schottky-clamped base-collector junction and an emitter directly connected to ground, and further including a first Schottky diode with an anode connected to the base of said first transistor and a cathode connected to said input, and a bias resistor connected between a source of voltage and the base of said first transistor; a second bipolar transistor having a Schottky-clamped base-collector junction, a grounded emitter, and including a second Schottky diode with an anode connected to the base of said second transistor and a cathode connected to said input, and further including a resistor connected between a source of voltage and the base of said second transistor, the collector of said second transistor being connected to said output; and a third transistor having a collector connected to a source of voltage, an emitter connected to said output, a base, and including a third Schottky diode with an anode connected to the base of said third transistor and a cathode connected to the collector of said first transistor, and further including a resistor connected between a source of voltage and the base of said third transistor.
Claim 11
Dependent Claim
30 words
The buffer circuit of claim 8 wherein said first, second and third Schottky diodes each include a forward threshold voltage less than the Schottky-clamped base-collector junction of said first transistor.
Claim 12
Dependent Claim
15 words
The buffer circuit of claim 8 wherein said source of voltage is about 2 volts.
Claim 13
Dependent Claim
31 words
The buffer of claim 1 further including a resistor directly connected between a voltage potential and the base of said second transistor to drive said second transistor in an on condition.
References Cited (Backward Citations)
No citation records indexed.
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1992-07-24 | 1993-01-23 | 1993-07-25 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1996-07-24 | 1997-01-23 | 1997-07-25 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2000-07-24 | 2001-01-23 | 2001-07-25 | $7700.00 | Window Closed / Lapsed |