US5210450A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Active selectable digital delay circuit
Assignee: St Clair Intellectual Property Consultants Inc
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Filing: 1992-06-29
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Granted: 1993-05-11
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Expires: 2012-06-29
Abstract
Abstract An active selectable digital delay circuit merges delay elements within a multiplexer to reduce power consumption, area and minimum delay. A current switch forms a basic element of a multiplexer. A group of current switches form an input to the multiplexer and another group of current switches form a control input to the multiplexer, the current switches being in a hierarchical tree configuration. Each input current switch has a resistor between an input voltage and the input to the current switch, the value of the resistor determining the amount of propagation delay between the input and output of the input current switch. With each input having a different resistance value, each input current switch provides a different amount of propagation delay for the input signal so that the delay of the output signal is determined by which input of the multiplexer is selected for output. Multiplexers may be cascaded to extend the selectable delay range between the input and output signals, with each output being input to a plurality of input resistors at the subsequent multiplexer in the cascade.
Inventors
- 👤 Peter B. Parkinson
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-29 12:09
CPC Classifications
H; H03; H03H; H03H11/00; H03H11/02; H03H11/26; H03H11/265; H03K; H03K17/00; H03K17/51; H03K17/56; H03K17/60; H03K17/603; H03K17/62; H03K17/6257; H03K17/6264; H03K5/00; H03K5/13; H03K5/131; H03K2005/00013; H03K2005/0015; H03K2005/00163; H03K2005/00176; H03K2005/00182; H03K2005/00228
Claims Analysis
Total Claims: 4
Claim 1
Independent Claim
216 words
A multiplexer for an active selectable digital delay circuit comprising: a plurality of current switches separated into a group of input current switches and a group of control current switches, each input current switch having a differential input for receiving a differential pair of input voltage signals, a differential output for providing a differential pair of output voltage signals and a control input coupled to one of the control current switches, the differential outputs being coupled together to form a single differential output, each input current switch having a charge delay characteristic at the differential input, and each control current switch having an input for receiving a control signal, wherein the control current switches are coupled to each other in a tree configuration so that a differential pair of output voltage signals from one of the input current switches as determined by the control signal received by the control current switches is selected as a delayed voltage signal at the single differential output; and resistors coupled between each differential pair of input voltage signals and the respective differential inputs of the input current switches for determining a unique propagation delay interval for each input current switch so that the propagation delay interval between the input and output voltage signals for each input current switch is different.
Claim 2
Dependent Claim
216 words
A multiplexer for an active selectable digital delay circuit comprising: a plurality of current switches separated into a group of input current switches and a group of control current switches, each input current switch having a differential input for receiving a differential pair of input voltage signals, a differential output for providing a differential pair of output voltage signals and a control input coupled to one of the control current switches, the differential outputs being coupled together to form a single differential output, each input current switch having a charge delay characteristic at the differential input, and each control current switch having an input for receiving a control signal, wherein the control current switches are coupled to each other in a tree configuration so that a differential pair of output voltage signals from one of the input current switches as determined by the control signal received by the control current switches is selected as a delayed voltage signal at the single differential output; and resistors coupled between each differential pair of input voltage signals and the respective differential inputs of the input current switches for determining a unique propagation delay interval for each input current switch so that the propagation delay interval between the input and output voltage signals for each input current switch is different.
Claim 3
Dependent Claim
155 words
An active selectable digital delay circuit comprising: a plurality of multiplexers coupled in cascade, each multiplexer having a plurality of inputs and an output, the output of each multiplexer except the last multiplexer in the cascade being input to a plurality of resistors coupled between the output and the respective inputs of a subsequent multiplexer with an input signal being applied to a plurality of resistors coupled to the inputs of the first multiplexer of the cascade, each resistor providing a different current value for each input of each multiplexer, and with a delayed signal being obtained from the output of the last multiplexer, a propagation delay between the input signal and the delayed signal being determined by a signal path between the input signal and the delayed signal; and means coupled to the multiplexers for controlling which input to each multiplexer is coupled to the output of that multiplexer to define the signal path.
Claim 4
Dependent Claim
155 words
An active selectable digital delay circuit comprising: a plurality of multiplexers coupled in cascade, each multiplexer having a plurality of inputs and an output, the output of each multiplexer except the last multiplexer in the cascade being input to a plurality of resistors coupled between the output and the respective inputs of a subsequent multiplexer with an input signal being applied to a plurality of resistors coupled to the inputs of the first multiplexer of the cascade, each resistor providing a different current value for each input of each multiplexer, and with a delayed signal being obtained from the output of the last multiplexer, a propagation delay between the input signal and the delayed signal being determined by a signal path between the input signal and the delayed signal; and means coupled to the multiplexers for controlling which input to each multiplexer is coupled to the output of that multiplexer to define the signal path.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1996-05-10 | 1996-11-09 | 1997-05-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 2000-05-10 | 2000-11-09 | 2001-05-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2004-05-10 | 2004-11-09 | 2005-05-11 | $7700.00 | Window Closed / Lapsed |