US4686392A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Multi-functional differential cascode voltage switch logic
Assignee: International Business Machines Corp
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Filing: 1985-10-30
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Granted: 1987-08-11
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Expires: 2005-10-30
Abstract
Abstract A differential cascode voltage switch (DCVS) logic circuit in which different DCVS logic blocks are connected in parallel to the output lines. Selection transistors connected to each logic block complete the conductivity path to ground. Only one selection transistor is selected at a time to thereby select the associated logic blocks. The circuit can be improved by merging portions of the different logic blocks which are identically connected to the output lines.
Inventors
- 👤 Tin-Chee Lo
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-30 17:47
CPC Classifications
H; H03; H03K; H03K19/00; H03K19/02; H03K19/173; H03K19/1733; H03K19/1738
Claims Analysis
Total Claims: 2
Claim 1
Independent Claim
167 words
A method of designing a logic circuit, comprising the steps of: providing at least three logic blocks, each logic block comprising a plurality of connected transistors controlled by input logic signals to selectively provide one and only one conductivity path between a selection node and the combination of two block output nodes; connecting two loads between a first predetermined reference potential and two logic signal output nodes; connecting said block output nodes to said logic signal output nodes, said logic signal output nodes providing complementary signals; connecting at least three selection transistors between respective selection nodes and a second predetermined reference potential, said selection transistors providing selection of one of said logic blocks; identifying at least two voltage nodes in at least two separate ones of said logic blocks having functionally equivalent sets of connections to said logic signal output nodes; connecting said identical voltage nodes; and eliminating transistors in a path from all but one of said identical voltage nodes to said logic signal output nodes.
Claim 2
Independent Claim
167 words
A method of designing a logic circuit, comprising the steps of: providing at least three logic blocks, each logic block comprising a plurality of connected transistors controlled by input logic signals to selectively provide one and only one conductivity path between a selection node and the combination of two block output nodes; connecting two loads between a first predetermined reference potential and two logic signal output nodes; connecting said block output nodes to said logic signal output nodes, said logic signal output nodes providing complementary signals; connecting at least three selection transistors between respective selection nodes and a second predetermined reference potential, said selection transistors providing selection of one of said logic blocks; identifying at least two voltage nodes in at least two separate ones of said logic blocks having functionally equivalent sets of connections to said logic signal output nodes; connecting said identical voltage nodes; and eliminating transistors in a path from all but one of said identical voltage nodes to said logic signal output nodes.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1990-08-10 | 1991-02-09 | 1991-08-11 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1994-08-10 | 1995-02-09 | 1995-08-11 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1998-08-10 | 1999-02-09 | 1999-08-11 | $7700.00 | Window Closed / Lapsed |