Series-coupled emitter coupled logic (ECL) circuit having a plurality of independently controllable current paths in a lower plane

Claim 1

In a series-coupled emitter-coupled logic circuit of the type having a first differential amplifier in a lower plane and second differential amplifiers in an upper plane, wherein the first differential amplifier includes a plurality of first transistors each having a base, an emitter and a collector, the emitters connected together for connection to a constant current supply, the base of one of said first transistors connected to a reference potential and the bases of the other first transistors serving to receive respective input signals of a first group of input signals for independently controlling the current paths through the respective transistors, wherein each second differential amplifier includes a pair of second transistors each having a base, an emitter and a collector, the emitters of each pair of second transistors connected to the collector of a respective controllable first transistor of the first differential amplifier, the base of one second transistor of each pair connected to a reference potential and the base of the other second transistor of each pair serving to receive a respective input signal of a second group of input signals for independently controlling the current paths through the respective transistors, wherein a first collector resistor connects the collectors of the controllable second transistors of the second differential amplifiers in the upper plane to an operating potential and a second collector resistor connects the collectors of the reference one first transistor in the lower plane and the referenced one second transistor of each second differential amplifier in the upper plane to the operating potential, wherein a first output transistor operates as an emitter follower for the controllable second transistors in the upper plane and a second output transistor operates as an emitter follower for the referenced transistors in the upper and lower planes, the first output transistor havIng a base connected in common with the collectors of the controllable transistors in the upper plane and to the first collector resistor, an emitter serving as a first output, and a collector connected in common with the first collector resistor and the operating potential, the second output transistor having a base connected in common with the collectors of the referenced transistors in the upper and lower planes and to the second collector resistor, an emitter serving as a second output, and a collector connected to the second collector resistor and to the operating potential, the improvement therein comprising: at least one additional second transistor in each second differential amplifier of the upper plane, each said additional second transistor having an emitter connected to the other emitters of the respective second differential amplifier and a collector connected to the collector of a controllable second transistor of the respective second differential amplifier to form an OR linkage, and a base for receiving an input signal from the first group of input signals, wherein the input signals applied to the bases of the additional second transistors excludes the input signal of the first group applied to the base of the respective controllable transistor which has its collector connected to the emitters of the respective second differential amplifier.