US4513283A — Latch circuits with differential cascode current …

Claim 1

Independent Claim 173 words

A set/reset latch circuit comprising in combination: (a) a cross-coupled pair of transistors arranged as a bistable device having first and second stable states and first and second output terminals; (b) a multi-level Differential Cascode Current Switch tree operable to develop set and reset control pulses for said circuit in response to logic input signals to switch said device respectively from said first state to said second state and vice versa; (c) a constant current source; (d) two load resistors, each of which is selectively connectable to said current source through said tree by said logic input signals; (e) means connecting said first and second output terminals to said load resistors; and (f) means for connecting said current source to said bistable device selectively through one of two different serial current paths of said tree to provide a current to one of said load resistors through one of said cross-coupled pair of transistors to hold said device in one of said stable states in the absence of said set and reset control pulses.

Claim 2

Dependent Claim 173 words

A set/reset latch circuit comprising in combination: (a) a cross-coupled pair of transistors arranged as a bistable device having first and second stable states and first and second output terminals; (b) a multi-level Differential Cascode Current Switch tree operable to develop set and reset control pulses for said circuit in response to logic input signals to switch said device respectively from said first state to said second state and vice versa; (c) a constant current source; (d) two load resistors, each of which is selectively connectable to said current source through said tree by said logic input signals; (e) means connecting said first and second output terminals to said load resistors; and (f) means for connecting said current source to said bistable device selectively through one of two different serial current paths of said tree to provide a current to one of said load resistors through one of said cross-coupled pair of transistors to hold said device in one of said stable states in the absence of said set and reset control pulses.

Claim 3

Dependent Claim 33 words

The latch circuit of claim 1 in which said logic input signals are differential signals and said tree includes at least one Differential Cascode Current Switch (DCCS) cell for each said differential signal.

Claim 4

Dependent Claim 26 words

The latch circuit of claim 2 in which said tree includes a predetermined number of different operable current paths between said current switch and said device.

Claim 5

Dependent Claim 30 words

The latch circuit of claim 3 in which some of said current paths include a delay component which has a signal delay corresponding to the signal delay of DCCS cell.

Claim 6

Dependent Claim 59 words

The latch circuit of claim 4 in which said DCCS cell at the first said level of said tree is adapted to receive a differential reset signal which, when active, functions to establish a reset current path to one said output terminals of said device to switch said device from said second stable state to said first stable state.

Claim 7

Dependent Claim 18 words

The latch circuit of claim 5 in which said reset current path includes two of said delay elements.

Claim 8

Dependent Claim 77 words

The latch circuit of claim 6 in which said tree further includes a second DCCS cell at a higher level adapted to receive a differential system data signal for establishing a set current path from the other of said load resistors through said second DCCS cell to said current source when said system data signal is a "1" and another path from from said device to said current source when said system data signal is a "0".

Claim 9

Dependent Claim 17 words

The latch circuit of claim 7 in which said set current path includes one said delay component.

Claim 10

Dependent Claim 61 words

The latch circuit of claim 7 in which said tree further includes a third DCCS cell at an intermediate said level which is adapted to receive a differential system clock signal that functions to connect said first cell to said third cell when said clock signal is active and said first cell to said device when said clock signal is inactive.

Claim 11

Dependent Claim 62 words

The latch circuit of claim 9 in which said system data signal supplied to said second cell switches said device to said second state when said clock signal is active, and said device remains in said second state until a reset signal is supplied to said device from said first cell regardless of subsequent active clock signals prior to said reset signal.

Claim 12

Dependent Claim 29 words

The latch circuit of claim 2 in which said tree further includes a Level Sensitive Scan Design input and means for entering scan in data selectively into said latch.

Claim 13

Dependent Claim 53 words

The latch circuit of claim 11 in which said tree further includes a scan in data DCCS cell for establishing selectively one of a pair of current paths from said current source through said LSSD port to said first and second output terminals in accordance with the value of said scan in data.

Claim 14

Dependent Claim 39 words

The latch circuit of claim 12 in which said input port includes a plurality of transistor switches each of which has an emitter coupled to said current source through the DCCS cell at the lowest level of said tree.

Claim 15

Dependent Claim 51 words

The latch circuit of claim 13 in which an LSSD clock signal is supplied to one of said transistor switches to connect said current source to said load resistors through said scan in data DCCS cell to switch said latch to one of said states corresponding to said scan in data.

Claim 16

Dependent Claim 42 words

The latch circuit of claim 14 in which a latch hold signal is supplied to another said transistor of said port to connect said current source to one of said load resistors through said device when said LSSD clock signal is inactive.

Claim 17

Dependent Claim 65 words

The latch circuit of claim 15 in which said LSSD port includes a third transistor for receiving a system clock signal for connecting said current source selectively to one of said output terminals through a DCCS cell adapted to receive system data to switch said device from the first state to the second state only when said system data and said system clock are active.

Claim 18

Dependent Claim 37 words

The latch circuit of claim 16 further including means connected to said LSSD input port to insure that one and only one of said plurality of transistors in said port is turned on at any one time.

Claim 19

Dependent Claim 60 words

The latch circuit of claim 1 further including a second latch circuit and means for connecting said first latch circuit to said second latch circuit to form a merged L1/L2 Shift Register Latch pair for LSSD testing, said connecting means including a DCCS cell for receiving a differential clock signal corresponding to the "B clock" of an LSSD testing system.

Claim 20

Dependent Claim 115 words

The latch circuit of claim 18 in which said tree includes a DCCS cell adapted to receive a differential mask signal and a four-input LSSD port including a plurality of switch transistors having their emitters coupled to said current source and means for supplying different signals to said switch transducers to operate said L2 latch as a polarity hold latch relative to said scan data and said L1 latch as a polarity hold latch relative to said scan in data and as a polarity hold latch relative to said system data when said differential mask signal is active and as a set/reset latch relative to said system data when said differential mask signal is inactive.

Claim 21

Dependent Claim 91 words

The combination recited in claim 18 in which said tree includes a four-input LSSD port including a plurality of switch transistors having their emitters coupled to said current source and means for supplying different signals to said switch transistor to operate said L2 latch as a polarity hold latch relative to scan in data and as a polarity hold latch relative to data transferred from said L1 latch, and said L1 latch as a polarity hold latch relative to scan in data and as a set/reset latch relative to system data.

Claim 22

Dependent Claim 63 words

The circuit recited in claim 20 in which said means for supplying different signals to said switch transistors comprises a plurality of DCCS tree units and a plurality of transistors serially connected together and associated with the output of each tree unit to translate the output of each said tree unit to a voltage level corresponding to level 1 of said LSSD port.

Annuity Stage	Window Opens	Payment Deadline	Surcharge Period Until	Estimated Fee	Status
3.5 Years (Year 4)	1988-04-22	1988-10-22	1989-04-23	$2000.00	Window Closed / Lapsed
7.5 Years (Year 8)	1992-04-22	1992-10-22	1993-04-23	$3760.00	Window Closed / Lapsed
11.5 Years (Year 12)	1996-04-22	1996-10-22	1997-04-23	$7700.00	Window Closed / Lapsed

Latch circuits with differential cascode current switch logic

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