US5173753A
Expired / Lapsed
US
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Inverted coplanar amorphous silicon thin film transistor which provides small contact capacitance and resistance
Assignee: Industrial Technology Research Institute
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Filing: 1992-01-27
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Granted: 1992-12-22
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Expires: 2012-01-27
Abstract
Abstract A process for manufacturing thin film transistors that have small source-drain areas, small gate-source parasitic capacitance C gs , and low contact resistance, comprising producing the gate of the transistor on a glass substrate, depositing a gate insulating layer, a thick undoped amorphous silicon layer and a top passivation layer successively on the substrate. The top passivation layer and the thick undoped amorphous silicon layer are then etched until the insulating layer is exposed.
Inventors
- 👤 Biing-Seng Wu
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-31 11:39
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0321; H10D30/0312; H10D30/0316; H10D30/60; H10D30/67; H10D30/674; H10D30/6757
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
240 words
A process for producing an inverted coplanar thin film transistor, comprising: (a) forming a gate for the transistor on a substrate, the gate having a top surface defined between edges; (b) depositing gate insulating, hydrogenated amorphous silicon, and top passivation layers successively on the substrate; (c) depositing and developing a photoresist layer on the top passivation layer to open source and drain windows in the photoresist layer; (d) etching the top passivation layer until two portions of the hydrogenated amorphous silicon layer are exposed; (e) etching the exposed two portions of the hydrogenated amorphous silicon layer until two portions of the gate insulating layer are exposed to form a source opening and a drain opening in the amorphous silicon layer, said source opening and drain opening each extending from the top of the top passivation layer to the bottom of the hydrogenated amorphous silicon layer, each of the openings extending between two side walls which face each other, both the top passivation layer and hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the openings each having a bottom at which is said gate insulating layer so that a projection of each of said bottoms onto said top surface is spaced from said edges of said gate; (f) removing the remaining photoresist; and (G) forming source and drain ohmic contact regions in said source and drain openings in said hydrogenated amorphous silicon layer.
Claim 2
Dependent Claim
240 words
A process for producing an inverted coplanar thin film transistor, comprising: (a) forming a gate for the transistor on a substrate, the gate having a top surface defined between edges; (b) depositing gate insulating, hydrogenated amorphous silicon, and top passivation layers successively on the substrate; (c) depositing and developing a photoresist layer on the top passivation layer to open source and drain windows in the photoresist layer; (d) etching the top passivation layer until two portions of the hydrogenated amorphous silicon layer are exposed; (e) etching the exposed two portions of the hydrogenated amorphous silicon layer until two portions of the gate insulating layer are exposed to form a source opening and a drain opening in the amorphous silicon layer, said source opening and drain opening each extending from the top of the top passivation layer to the bottom of the hydrogenated amorphous silicon layer, each of the openings extending between two side walls which face each other, both the top passivation layer and hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the openings each having a bottom at which is said gate insulating layer so that a projection of each of said bottoms onto said top surface is spaced from said edges of said gate; (f) removing the remaining photoresist; and (G) forming source and drain ohmic contact regions in said source and drain openings in said hydrogenated amorphous silicon layer.
Claim 3
Dependent Claim
20 words
The process for producing a thin film transistor of claim 1, comprising forming the gate insulating layer of silicon nitride.
Claim 4
Dependent Claim
20 words
The process for producing a thin film transistor of claim 1, comprising forming the gate insulating layer of silicon oxide.
Claim 5
Dependent Claim
20 words
The process for producing a thin film transistor of claim 1 comprising forming the top passivation layer of silicon nitride.
Claim 6
Dependent Claim
20 words
The process for producing a thin film transistor of claim 1 comprising forming the top passivation layer of silicon oxide.
Claim 7
Dependent Claim
20 words
The process for producing a thin film transistor of claim 1 comprising etching the top passivation layer by dry etching.
Claim 8
Dependent Claim
21 words
The process for producing a thin film transistor of claim 1 comprising etching the hydrogenated amorphous silicon layer by dry etching.
Claim 9
Dependent Claim
22 words
The process for producing a thin film transistor of claim 1 wherein the step (S) includes depositing a conductive-doped amorphous silicon layer.
Claim 10
Dependent Claim
184 words
The process for producing a thin film transistor of claim 8 wherein said source and drain ohmic contact regions define an active region therebetween, said process further comprising: (h) depositing, exposing and developing a photoresist layer on the active region; (i) etching the conductive-doped amorphous silicon layer, the top passivation layer, and the hydrogenated amorphous silicon layer until a portion of the gate insulating layer outside the active region is exposed; (j) removing the photoresist layer; (k) depositing, exposing and developing a second photoresist layer on the gate insulating layer; (l) etching the gate insulating layer through the second photoresist layer until a metal contact region of the gate is exposed; (m) removing the remaining second photoresist layer; (n) depositing contact metal; (o) depositing and developing a third photoresist layer on the contact metal; (p) etching the contact metal through the third photoresist layer to form the connection of the gate and to form source/drain contact electrodes and successively etching the conductive-doped amorphous silicon layer between source and drain until the top passivation layer is exposed; and (q) removing the residual third photoresist layer.
Claim 11
Dependent Claim
165 words
A process for producing an inverted coplanar thin film transistor, comprising the steps of: (a) forming a layered structure comprising a substrate, a gate on the substrate, successive layers on the substrate and gate, the successive layers constituting a gate insulating layer, a hydrogenated amorphous silicon layer and a top passivation layer, the gate having a top surface facing the gate insulating layer and having edges which define the top surface; and (b) forming a source and a drain ohmic contact region in respective openings through the hydrogenated amorphous silicon and top passivation layers, each of the openings extending between two side walls which face each other, both the top passivation layer and the hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the openings each having a respective bottom at which is the gate insulating layer so that a projection of each of the bottoms onto the top surface is spaced from the edges of the gate.
Claim 12
Dependent Claim
165 words
A process for producing an inverted coplanar thin film transistor, comprising the steps of: (a) forming a layered structure comprising a substrate, a gate on the substrate, successive layers on the substrate and gate, the successive layers constituting a gate insulating layer, a hydrogenated amorphous silicon layer and a top passivation layer, the gate having a top surface facing the gate insulating layer and having edges which define the top surface; and (b) forming a source and a drain ohmic contact region in respective openings through the hydrogenated amorphous silicon and top passivation layers, each of the openings extending between two side walls which face each other, both the top passivation layer and the hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the openings each having a respective bottom at which is the gate insulating layer so that a projection of each of the bottoms onto the top surface is spaced from the edges of the gate.
Claim 13
Dependent Claim
27 words
A process as in claim 10, wherein the step of forming a source and a drain ohmic contact region includes providing doped amorphous silicon in the openings.
Claim 14
Dependent Claim
152 words
An inverted coplanar thin transistor, comprising: a layered structure comprising a substrate, a gate on the substrate, successive layers on the substrate and gate constituting a gate insulating layer, a hydrogenated amorphous silicon layer and a top passivation layer, the gate having a top surface facing the gate insulating layer and having edges which define the top surface; and a source and a drain ohmic contact region each in a respective opening through the hydrogenated amorphous silicon and top passivation layers, each of the openings extending between two side walls which face each other, both the top passivation layer and the hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the openings each having a respective bottom at which is the gate insulating layer so that a projection of each of the bottoms onto the top surface is spaced from the edges of the gate.
Claim 15
Dependent Claim
152 words
An inverted coplanar thin transistor, comprising: a layered structure comprising a substrate, a gate on the substrate, successive layers on the substrate and gate constituting a gate insulating layer, a hydrogenated amorphous silicon layer and a top passivation layer, the gate having a top surface facing the gate insulating layer and having edges which define the top surface; and a source and a drain ohmic contact region each in a respective opening through the hydrogenated amorphous silicon and top passivation layers, each of the openings extending between two side walls which face each other, both the top passivation layer and the hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the openings each having a respective bottom at which is the gate insulating layer so that a projection of each of the bottoms onto the top surface is spaced from the edges of the gate.
Claim 16
Dependent Claim
15 words
A structure as in claim 12, wherein the ohmic contact region is doped amorphous silicon.
Claim 17
Dependent Claim
182 words
A process for producing an inverted coplanar thin film transistor, comprising the steps of: (a) forming a layered structure comprising a substrate, a gate on the substrate, successive layers on the substrate and gate, the successive layers constituting a gate insulating layer, a hydrogenated amorphous silicon layer and a top passivation layer, the hydrogenated amorphous silicon and top passivation layers having two openings each extending between a respective two side walls which face each other, both the top passivation layer and the hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the gate having a top surface and having edges which define the top surface, the openings each having a respective bottom at which is the gate insulating layer so that a projection of each of the bottoms onto the top surface is spaced from the edges of the gate; and (b) forming a source and a drain ohmic contact region, the source ohmic contact region being in one of the openings and the drain ohmic contact region being in the other of the openings.
Claim 18
Dependent Claim
182 words
A process for producing an inverted coplanar thin film transistor, comprising the steps of: (a) forming a layered structure comprising a substrate, a gate on the substrate, successive layers on the substrate and gate, the successive layers constituting a gate insulating layer, a hydrogenated amorphous silicon layer and a top passivation layer, the hydrogenated amorphous silicon and top passivation layers having two openings each extending between a respective two side walls which face each other, both the top passivation layer and the hydrogenated amorphous silicon layer being at both of the side walls of each of the openings, the gate having a top surface and having edges which define the top surface, the openings each having a respective bottom at which is the gate insulating layer so that a projection of each of the bottoms onto the top surface is spaced from the edges of the gate; and (b) forming a source and a drain ohmic contact region, the source ohmic contact region being in one of the openings and the drain ohmic contact region being in the other of the openings.
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-22 | 1996-06-22 | 1996-12-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-22 | 2000-06-22 | 2000-12-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-22 | 2004-06-22 | 2004-12-22 | $7700.00 | Window Closed / Lapsed |