← Back to Patent Explorer
US4885616A Expired / Lapsed US ⏱️ 0.0 years remaining

Thin film display device with thin amorphous channel

Assignee: LG Display Co Ltd
•
Filing: 1987-08-21
•
Granted: 1989-12-05
•
Expires: 2007-08-21
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract A picture element selective transistor with a staggered structure, for an active matrix type thin film liquid crystal display device, has a channel region layer thinner than 1000 Å so that the OFF electric current at the light irradiating time is reduced, whereby it is possible to omit a light-shielding layer, and simplify manufacturing process.

Inventors

  • 👤 Masahiko Ohta

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-10-25 14:48
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746

Claims Analysis

Total Claims: 10
Claim 1
Independent Claim 137 words
In a thin film display device having a liquid crystal panel and a picture element selective transistor formed on a substrate, said picture element selective transistor comprising: a gate region formed on the substrate; a first insulating layer formed on the gate region and the substrate; a channel region layer composed of an undoped amorphous silicon single layer and having a thickness less than 1000 Å, the channel region layer being formed on the first insulating layer; a second insulating layer formed on the channel region layer and the first insulating layer, the second insulating layer being partially removed for exposing spaced-apart top parts of the channel region layer; a semi-conductive layer selectively formed on the exposed top parts of the channel region layer to define source and drain regions; and electrodes formed on the semi-conductive layer.
Claim 2
Dependent Claim 137 words
In a thin film display device having a liquid crystal panel and a picture element selective transistor formed on a substrate, said picture element selective transistor comprising: a gate region formed on the substrate; a first insulating layer formed on the gate region and the substrate; a channel region layer composed of an undoped amorphous silicon single layer and having a thickness less than 1000 Å, the channel region layer being formed on the first insulating layer; a second insulating layer formed on the channel region layer and the first insulating layer, the second insulating layer being partially removed for exposing spaced-apart top parts of the channel region layer; a semi-conductive layer selectively formed on the exposed top parts of the channel region layer to define source and drain regions; and electrodes formed on the semi-conductive layer.
Claim 3
Dependent Claim 25 words
In a thin film display device according to claim 1; further comprising a high-melting point material layer formed between the semi-conductive layer and the electrodes.
Claim 4
Dependent Claim 149 words
A thin film transistor for driving a picture element of an active matrix type display device, comprising: a substrate; a gate region disposed on the substrate; an insulating layer disposed on the gate region; a channel region layer disposed on the insulating layer and opposed to the gate region to define a channel thereon, the channel region layer being composed of an undoped amorphous silicon single layer and having a thickness less than 1000 Å so as to effectively limit the generation of photoelectric current therein caused by light incident on the channel region; and drain and source regions disposed separately from each other in contact with the top portion of the channel region for supplying a drive current to the channel region, the drain and source regions each being comprised of a semi-conductive layer in contact with the channel region and an electrode layer on the semi-conductive layer.
Claim 5
Dependent Claim 149 words
A thin film transistor for driving a picture element of an active matrix type display device, comprising: a substrate; a gate region disposed on the substrate; an insulating layer disposed on the gate region; a channel region layer disposed on the insulating layer and opposed to the gate region to define a channel thereon, the channel region layer being composed of an undoped amorphous silicon single layer and having a thickness less than 1000 Å so as to effectively limit the generation of photoelectric current therein caused by light incident on the channel region; and drain and source regions disposed separately from each other in contact with the top portion of the channel region for supplying a drive current to the channel region, the drain and source regions each being comprised of a semi-conductive layer in contact with the channel region and an electrode layer on the semi-conductive layer.
Claim 6
Dependent Claim 16 words
A thin film transistor according to claim 3; wherein the insulating layer is composed of SiN.
Claim 7
Dependent Claim 39 words
A thin film transistor according to claim 3; wherein the drain and source regions further comprise an intermediate metal layer disposed between the semi-conductive layer and the electrode layer, the intermediate metal layer being composed of high-melting point metal.
Claim 8
Dependent Claim 27 words
A thin film transistor according to claim 5; wherein the electrode layer is composed of Al and the intermediate metal layer is composed of Cr or Mo.
Claim 9
Dependent Claim 21 words
A thin film transistor according to claim 3; wherein the active matrix type display device comprises a liquid crystal display device.
Claim 10
Dependent Claim 22 words
A thin film transistor according to claim 3; wherein the top portion of the channel region is free of a light-shielding layer.

References Cited (Backward Citations)

US3840695A Cited
US4065781A Cited
US4040073A Cited
US4752814A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1992-12-04 1993-06-05 1993-12-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1996-12-04 1997-06-05 1997-12-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2000-12-04 2001-06-05 2001-12-05 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag