Patent US3184397A successfully refreshed from Google Patents.
US4587720A
Expired / Lapsed
US
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Process for the manufacture of a self-aligned thin-film transistor
Assignee: Commissariat à l'Énergie Atomique et Aux Énergies Alternatives
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Filing: 1984-10-10
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Granted: 1986-05-13
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Expires: 2004-10-10
Abstract
Abstract The process consists in producing the grid (4) of the transistor on a glass substrate (2), depositing an insulating layer (6) on the substrate and grid, depositing a thick layer (8) of hydrogenated amorphous silicon on the insulating layer, depositing on the silicon layer a layer (10) of positive photosensitive resin sensitive to light of a wavelength greater than 550 nm, irradiating the resin layer through the substrate, the grid serving as a mask for the irradiation, developing the resin, etching the silicon layer until the insulating layer is bared, the remanent resin serving as a mask for the etching, depositing the layers permitting the making of the electrical contacts and the electrodes of the source and of the drain, eliminating the remanent resin (10a), and etching the electrodes of the source and of the drain.
Inventors
- 👤 Andre Chenevas-Paule
- 👤 Bernard Diem
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 09:53
CPC Classifications
H; H10; H10P; H10P76/00; H10P76/20; H10P76/204; H10P76/2041; H10D; H10D30/00; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6746; Y; Y10; Y10S; Y10S148/00; Y10S148/091; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/949
Claims Analysis
Total Claims: 6
Claim 1
Independent Claim
163 words
Process for producing a thin-film self-aligned grid transistor, comprising the following steps: (a) forming the grid of the transistor on a glass substrate; (b) depositing an insulating layer on the substrate and a gate; (c) depositing a layer of hydrogenated amorphous silicon on said insulating layer in an amount sufficient to provide a thickness of from about 150 to 300 namometers; (d) depositing on said silicon layer a layer positive photosensitive resin sensitive to light and having a wavelength greater than 550 nanometers; (e) irradiating said resin layer through said substrate, the gate serving as a mask for the irradiation; (f) developing the resin layer leading to the elimination of the irradiated zones of the said resin layer; (g) etching said silicon layer until said insulating layer is laid bare, the residual resin serving as a mask for the said etching; (h) connecting the electrical contacts and the electrodes of the source and drain of the transistor; and (i) eliminating the residual resin;
Claim 2
Dependent Claim
163 words
Process for producing a thin-film self-aligned grid transistor, comprising the following steps: (a) forming the grid of the transistor on a glass substrate; (b) depositing an insulating layer on the substrate and a gate; (c) depositing a layer of hydrogenated amorphous silicon on said insulating layer in an amount sufficient to provide a thickness of from about 150 to 300 namometers; (d) depositing on said silicon layer a layer positive photosensitive resin sensitive to light and having a wavelength greater than 550 nanometers; (e) irradiating said resin layer through said substrate, the gate serving as a mask for the irradiation; (f) developing the resin layer leading to the elimination of the irradiated zones of the said resin layer; (g) etching said silicon layer until said insulating layer is laid bare, the residual resin serving as a mask for the said etching; (h) connecting the electrical contacts and the electrodes of the source and drain of the transistor; and (i) eliminating the residual resin;
Claim 3
Dependent Claim
23 words
A process according to claim 1, wherein the photosensitive resin is sensitive to light having a wavelength of the order of 600 nanometers.
Claim 4
Dependent Claim
68 words
A process according to claim 1, wherein step (h) comprises: depositing a layer of n+ type amorphous silicon on the entire structure; depositing a conducting layer on the type n+ silicon layer; eliminating the regions respectively of the conducting layer and of the type n+ silicon layer situated in line with said grid; and making the electrodes of the source and of the drain in said conducting layer.
Claim 5
Dependent Claim
16 words
A process according to claim 1, wherein said insulating layer is a layer of silicon dioxide.
Claim 6
Dependent Claim
15 words
A process according to claim 3, wherein said conducting layer is a layer of chromium.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1989-05-12 | 1989-11-11 | 1990-05-13 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1993-05-12 | 1993-11-11 | 1994-05-13 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 1997-05-12 | 1997-11-11 | 1998-05-13 | $7700.00 | Window Closed / Lapsed |