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US4685195A Expired / Lapsed US ⏱️ 0.0 years remaining

Method for the manufacture of at least one thin film field effect transistor

Assignee: Thales SA
•
Filing: 1985-06-11
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Granted: 1987-08-11
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Expires: 2005-06-11
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Abstract

Abstract The invention relates to a method for the manufacture of thin film field effect transistors of the type having self-alignment of the electrodes and obtained on an insulating substrate. The method comprises two constructional variants making it possible to produce a submicron gate electrode determining a minimum channel length. The invention is applicable to the field of large surface or area microelectronics and in particular to the control and addressing of a flat liquid crystal screen or an image sensor.

Inventors

  • 👤 Nicolas Szydlo
  • 👤 Francois Boulitrop

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-06 08:11
CPC Classifications
H; H10; H10D; H10D86/00; H10D86/01; H10D86/021; H10D86/0231; H10D30/00; H10D30/01; H10D30/021; H10D30/031; H10D30/0312; H10D30/0316; H10D30/0321; H10D30/60; H10D30/67; H10D30/6729; H10D30/673; H10D30/6732; H10D30/674; H10D30/6741; H10D30/6743; H10D30/6745; H10D30/6746; H10D86/40; H10D86/60; Y; Y10; Y10S; Y10S438/00; Y10S438/942; Y10S438/948; Y10S438/949

Claims Analysis

Total Claims: 15
Claim 1
Independent Claim 245 words
A method for the manufacture of at least one thin film field effect transistor of the type having self-alignment of the electrodes, the transistor being obtained from successive deposits on a first face of a transparent, insulating substrate, wherein the method comprises the following stages: first stage: deposits on the first face of the substrate of a first metal coating and a coating of a first material, second stage: formation of a mesa of said first material, third stage: deposition of a coating of a second material of given thickness, fourth stage: etching said second material so as to only leave a first shoulder of the second material on the side or edge of the mesa, fifth stage: etching the mesa until it has been completely eliminated, sixth stage: etching the first metal coating so as to only leave a second metal shoulder protected by the first shoulder, seventh stage: etching the first shoulder until it has been completely eliminated, eighth stage: successive deposits of a transparent grid insulant coating and a thin coating of a transparent semiconductor material, ninth stage: deposit of a photosensitive resin coating, irradiation of the resin from the second face of the substrate and elimination of the irradiated part of the resin, tenth stage: formation of source and drain ohmic regions, eleventh stage: deposit of a second metal coating and removal of resin and second metal coating on the resin, twelfth stage: delimitation of the gate, source and drain electrodes.
Claim 2
Independent Claim 245 words
A method for the manufacture of at least one thin film field effect transistor of the type having self-alignment of the electrodes, the transistor being obtained from successive deposits on a first face of a transparent, insulating substrate, wherein the method comprises the following stages: first stage: deposits on the first face of the substrate of a first metal coating and a coating of a first material, second stage: formation of a mesa of said first material, third stage: deposition of a coating of a second material of given thickness, fourth stage: etching said second material so as to only leave a first shoulder of the second material on the side or edge of the mesa, fifth stage: etching the mesa until it has been completely eliminated, sixth stage: etching the first metal coating so as to only leave a second metal shoulder protected by the first shoulder, seventh stage: etching the first shoulder until it has been completely eliminated, eighth stage: successive deposits of a transparent grid insulant coating and a thin coating of a transparent semiconductor material, ninth stage: deposit of a photosensitive resin coating, irradiation of the resin from the second face of the substrate and elimination of the irradiated part of the resin, tenth stage: formation of source and drain ohmic regions, eleventh stage: deposit of a second metal coating and removal of resin and second metal coating on the resin, twelfth stage: delimitation of the gate, source and drain electrodes.
Claim 3
Dependent Claim 19 words
A manufacturing method according to claim 1, wherein the first metal coating is an aluminium coating deposited by evaporation.
Claim 4
Dependent Claim 24 words
A manufacturing method according to claim 1, wherein the first metal coating is a chromium coating or a nickel-chromium alloy coating deposited by evaporation.
Claim 5
Dependent Claim 17 words
A manufacturing method according to claim 1, wherein the first material is silicon dioxide SiO 2 .
Claim 6
Dependent Claim 23 words
A manufacturing method according to claim 1, wherein the second material is of amorphous or polycyrstalline silicon deposited by plasma-assisted CVD or LPCVD.
Claim 7
Dependent Claim 24 words
A manufacturing method according to claim 1, wherein the etching of the second material formed during the fourth stage is reactive ion etching (RIE).
Claim 8
Dependent Claim 29 words
A maufacturing method according to claim 1, wherein the gate insulant is of silicon dioxide SiO 2 , silicon oxynitride SiON or silicon nitride Si 3 N 4 .
Claim 9
Dependent Claim 23 words
A manufacturing method according to claim 1, wherein the semiconductor material deposited in the eighth stage is of amorphous silicon or polycrystalline silicon.
Claim 10
Dependent Claim 25 words
A manufacturing method according to claim 1, wherein the ohmic regions of the tenth stage are obtained by the deposit of n doped semiconductor material.
Claim 11
Dependent Claim 23 words
A manufacturing method according to claim 1, wherein the ohmic regions of the tenth stage are obtained by ion implantation followed by annealing.
Claim 12
Dependent Claim 20 words
A manufacturing method according to claim 10, wherein implantation of the semiconductor layer is realised by phosphorous or arsenic ions.
Claim 13
Dependent Claim 18 words
A manufacturing method according to claim 10, wherein ion implantation is carried out according to different energy levels.
Claim 14
Dependent Claim 18 words
A manufacturing method according to claim 1, wherein the second metal coating is of aluminium deposited by evaporation.
Claim 15
Dependent Claim 50 words
A manufacturing method according to claim 1, wherein during the eighth stage, a coating of a passivation insulant is deposited on the semiconductor coating and wherein, at the end of the ninth stage, that part of the passivation insulant not protected by the non-irradiated part of the resin is eliminated.

References Cited (Backward Citations)

US4174217A Cited
US4393572A Cited
EP0090661A2 Cited
US4551905A Cited
US4542577A Cited
US4532698A Cited

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1990-08-10 1991-02-09 1991-08-11 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1994-08-10 1995-02-09 1995-08-11 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 1998-08-10 1999-02-09 1999-08-11 $7700.00 Window Closed / Lapsed

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