Patent US5170230A successfully refreshed from Google Patents.
US5170230A
Expired / Lapsed
US
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Semiconductor device and production method thereof
Assignee: Fujitsu Ltd
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Filing: 1990-05-10
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Granted: 1992-12-08
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Expires: 2010-05-10
Abstract
Abstract A semiconductor device includes an InP substrate, an intrinsic InGaAs channel layer formed on the InP substrate and lattice matched to the InP substrate, a doped GaAsSb carrier supply layer formed on the intrinsic InGaAs channel layer and lattice matched to the InP substrate, a gate electrode formed on the doped GaAsSb carrier supply layer, and a source electrode and a drain electrode which are respectively formed on the doped GaAsSb carrier supply layer and located on both sides of the gate electrode.
Inventors
- 👤 Masahiko Takikawa
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-11-01 13:04
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D30/01; H10D30/015; H10D30/473; H10D30/4732; H10D62/00; H10D62/80; H10D62/82; H10D62/824; H10D84/00; H10D84/80; H10D84/86; H10P; H10P50/00; H10W; H10W20/00; H10W20/01; H10W20/071; H10W20/074; Y; Y10; Y10S; Y10S148/00; Y10S148/005
Claims Analysis
Total Claims: 10
Claim 1
Independent Claim
148 words
A semiconductor device comprising: an InP substrate; an intrinsic InGaAs channel layer formed on said InP substrate and lattice matched to said InP substrate; a first doped GaAs Sb carrier supply layer formed on said intrinsic InGaAs channel layer and lattice matched to said InP substrate; an etching stopper layer formed on said first doped GaAsSb carrier supply layer; a second doped GaAsSb carrier supply layer formed on said etching stopper layer; a first gate electrode having first and second opposite sides, and formed on said second doped GaAsSb carrier supply layer and defining corresponding first and second portions of said doped GaAsSb carrier supply layer; and a first source electrode and a first drain electrode which are respectively formed on said first and second portions of said second doped GaAsSb carrier supply layer and located adjacent said first and second opposite sides of said first gate electrode.
Claim 2
Dependent Claim
148 words
A semiconductor device comprising: an InP substrate; an intrinsic InGaAs channel layer formed on said InP substrate and lattice matched to said InP substrate; a first doped GaAs Sb carrier supply layer formed on said intrinsic InGaAs channel layer and lattice matched to said InP substrate; an etching stopper layer formed on said first doped GaAsSb carrier supply layer; a second doped GaAsSb carrier supply layer formed on said etching stopper layer; a first gate electrode having first and second opposite sides, and formed on said second doped GaAsSb carrier supply layer and defining corresponding first and second portions of said doped GaAsSb carrier supply layer; and a first source electrode and a first drain electrode which are respectively formed on said first and second portions of said second doped GaAsSb carrier supply layer and located adjacent said first and second opposite sides of said first gate electrode.
Claim 3
Dependent Claim
121 words
The semiconductor device as claimed in claim 1, further comprising: a second gate electrode having first and second opposite sides, and formed on said etching stopper layer; a second source electrode and a second drain electrode respectively formed on said second doped GaAsSb carrier supply layer and located adjacent said first and second opposite sides of said second electrode; and an isolation region which isolates first and second regions, said first region including a depletion type high electron mobility transistor having said first gate electrode, and said first source electrode and said first drain electrode, and said second region including an enhancement type high electron mobility transistor having said second gate electrode, said second source electrode and said second drain electrode.
Claim 4
Dependent Claim
34 words
The semiconductor device as claimed in claim 1 wherein said first and second doped GaAsSb carrier supply layers are made of n-type GaAsSb, and said etching stopper layer is made of an n-type material.
Claim 5
Dependent Claim
31 words
The semiconductor device as claimed in claim 1 wherein said etching stopper layer has a thickness of approximately 20 Å and an impurity density of approximately 1.5×10 18 cm -3 .
Claim 6
Dependent Claim
31 words
The semiconductor device as claimed in claim 4 wherein said etching stopper layer is made of a material such that said etching stopper layer is lattice matched to said InP substrate.
Claim 7
Dependent Claim
28 words
The semiconductor device as claaimed in claim 5, wherein said etching stopper layer is made of a material selected from the group consisting of AlInAs, InP and InGaAs.
Claim 8
Dependent Claim
32 words
The semiconductor device as claimed in claim 4 wherein said etching stopper layer is made of a material such that said etching stopper layer is not lattice matched to said InP substrate.
Claim 9
Dependent Claim
27 words
The semiconductor device as claimed in claim 7 wherein said etching stopper layer is made of a material selected from a group including AlInGaAs, AlGaAs and InGaP.
Claim 10
Dependent Claim
41 words
The semiconductor device as claimed in claim 4 wherein said first and second doped GaAsSb carrier supply layers respectively have a thickness in a range of approximately 200 to 300 Å and an impurity density of approximately 1.5×10.sup.˜ cm -3 .
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USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1995-12-08 | 1996-06-08 | 1996-12-08 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1999-12-08 | 2000-06-08 | 2000-12-08 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2003-12-08 | 2004-06-08 | 2004-12-08 | $7700.00 | Window Closed / Lapsed |