EP0175437A1
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EP
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Production of GaAs enhancement and depletion mode HEMT's
Assignee: Fujitsu Ltd
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Filing: 1985-04-30
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Granted: —
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Expires: 2005-04-30
Abstract
Abstract A semiconductor device, which comprises an E-mode FET and a D-mode FET and utilizes a two-dimensional electron gas, comprises a semi-insulating semiconductor substrate (1), a channel layer (2), an electron-supply layer (3), a third layer (4), a first etching-stoppable layer (5), a fifth layer (6), and a second etching-stoppable layer (7), which layers are formed in sequence on the substrate (1). An etching process for forming grooves (22E, 22D, 45E, 45D) of gate electrodes (23, 24, 46, 47) of the FET's comprises a first etching treatment removing the first etching-stoppable layer portion (5) in the E-mode FET region and the second etching-stoppable layer portion (7) in the D-mode FET region, and a second etching treatment removing the third layer portion (4) in the E-mode FET region and the fifth layer portion (6) and using an etchant different from that used in the first etching treatment. In the second etching treatment, reactive ion etching method using a CC1 2 F 2 etchant gas is adopted, since GaAs can be thereby rapidly etched as compared with AlGaAs used for the etching-stoppable layer material.
Inventors
- 👤 Masahisa Suzuki
- 👤 Takashi Mimura
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-06 13:23
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/246; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0158; H10D84/0163; H10D84/02; H10D84/05; H10P50/242; H10D84/03; H10D84/038; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 19
Claim 1
Independent Claim
372 words
A method of producing a semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor and utilizes a two-dimensional electron gas, comprising the steps of: (a) forming a first semiconductor layer (2) of a channel layer, in which the two-dimensional electron gas is generatable, on a semi-insulating semiconductor substrate (1); (b) forming a second semiconductor layer (3) of an electron-supply layer on the first insulating layer (2); (c) forming a third semiconductor layer (4) of an adjusting layer for the threshold voltage of the depletion-mode transistor on the second semiconductor layer (3); (d) forming a fourth semiconductor layer (5) of a first contact layer on the third semiconductor layer; (e) forming a fifth semiconductor layer (6) of a contact layer on the fourth semiconductor layer (5); (f) forming a sixth layer of a second etching-stoppable layer on the fifth semiconductor layer (6); (g) forming a masking layer (16) having openings (17E, 17D) corresponding to gates of the enhancement-mode and depletion-mode transistors; (h) etching the sixth to third layers in the E-mode FET region and the sixth anf fifth layers in the D-mode FET region to form grooves (22E, 22D, 45E, 45D) for gate electrodes (23, 24, 46, 47) of the E-mode and D-mode FET's; and (i) forming the gate electrodes by filling the grooves with a conductove material; characterized in that the etching step (h) comprises the steps of: (i) exposing a portion of the fourth semiconductor layer (5) in the enhancement-mode transistor region and a portion of the sixth layer (7) in the depletion-mode transistor region through the openings (17E, 17D, 40E, 40D) in said masking layer (16, 39); (ii) performing a first etching treatment through the openings (17E, 17D, 40E, 40D) in said masking layer to expose a portion of the third semiconductor layer (4) in the enhancement-mode transistor region and a portion of the fifth semiconductor layer in the (6) depletion-mode transistor region; and (iii) performing a second etching treatment different from the first etching treatment to expose a portion of the second semiconductor layer (3) in the enhancement-mode transistor region and a portion of the fourth semiconductor layer (5) in the depletion-mode transistor region to form grooves (17E, 17D, 40E, 40D) for gate electrodes of the FET's.
Claim 2
Independent Claim
372 words
A method of producing a semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor and utilizes a two-dimensional electron gas, comprising the steps of: (a) forming a first semiconductor layer (2) of a channel layer, in which the two-dimensional electron gas is generatable, on a semi-insulating semiconductor substrate (1); (b) forming a second semiconductor layer (3) of an electron-supply layer on the first insulating layer (2); (c) forming a third semiconductor layer (4) of an adjusting layer for the threshold voltage of the depletion-mode transistor on the second semiconductor layer (3); (d) forming a fourth semiconductor layer (5) of a first contact layer on the third semiconductor layer; (e) forming a fifth semiconductor layer (6) of a contact layer on the fourth semiconductor layer (5); (f) forming a sixth layer of a second etching-stoppable layer on the fifth semiconductor layer (6); (g) forming a masking layer (16) having openings (17E, 17D) corresponding to gates of the enhancement-mode and depletion-mode transistors; (h) etching the sixth to third layers in the E-mode FET region and the sixth anf fifth layers in the D-mode FET region to form grooves (22E, 22D, 45E, 45D) for gate electrodes (23, 24, 46, 47) of the E-mode and D-mode FET's; and (i) forming the gate electrodes by filling the grooves with a conductove material; characterized in that the etching step (h) comprises the steps of: (i) exposing a portion of the fourth semiconductor layer (5) in the enhancement-mode transistor region and a portion of the sixth layer (7) in the depletion-mode transistor region through the openings (17E, 17D, 40E, 40D) in said masking layer (16, 39); (ii) performing a first etching treatment through the openings (17E, 17D, 40E, 40D) in said masking layer to expose a portion of the third semiconductor layer (4) in the enhancement-mode transistor region and a portion of the fifth semiconductor layer in the (6) depletion-mode transistor region; and (iii) performing a second etching treatment different from the first etching treatment to expose a portion of the second semiconductor layer (3) in the enhancement-mode transistor region and a portion of the fourth semiconductor layer (5) in the depletion-mode transistor region to form grooves (17E, 17D, 40E, 40D) for gate electrodes of the FET's.
Claim 3
Dependent Claim
66 words
A method according to claim 1, wherein the second and fourth semiconductor layers (3, 4) are of a semiconductor material and the third and fifth semiconductor layers (4, 6) are of another semiconductor material, and in the second etching treatment step (iii) the third and fifth semiconductor layers (4, 6) are easily etched and the second and fourth semiconductor layers (3, 5) are not substantially etched.
Claim 4
Dependent Claim
51 words
A method according to claim 2, wherein the second and fourth semiconductor layers (3, 5) are of AlGaAs and the third and fifth semiconductor layers (4, 6) are of GaAs, and the second etching treatment is a reactive ion etching using an etchant gas comprising CC 1 2 F 2 .
Claim 5
Dependent Claim
15 words
A method according to claim 1, wherein the sixth layer is of a semiconductor material.
Claim 6
Dependent Claim
43 words
A method according to claim 4, wherein the sixth semiconductor layer (7) is of the same material as the fourth semiconductor layer (5) and in the first etching treatment step (ii) at least the fourth and sixth semiconductor layers (5, 7) are etched.
Claim 7
Dependent Claim
23 words
A method according to claim 4 further comprising the step of forming a seventh semiconductor layer (8) on the sixth semiconductor layer (7).
Claim 8
Dependent Claim
37 words
A method according to claim 14, wherein the seventh, fifth and third semiconductor layers (8, 6, 4) comprise the same first material, and sixth, fourth and second semiconductor layers (6, 5, 11) comprise the same second material.
Claim 9
Dependent Claim
32 words
A method according to claim 6 further comprising the step of selectively etching portions of the seventh and sixth semiconductor layers (8, 7) in the enhancement-mode transistor region before the step (g).
Claim 10
Dependent Claim
45 words
A method according to claim 8, wherein, in the step (h), the third etching treatment is performed for etching the fifth semiconductor layer (6) in the seventh semiconductor layer (8) in the depletion-mode transistor region through the openings (17E, 17D) of said masking layer (16).
Claim 11
Dependent Claim
22 words
A method according to claim 9, wherein the third etching treatment is performed in the same manner as the second etching treatment.
Claim 12
Dependent Claim
45 words
A method according to claim 10, wherein the first meterial comprises GaA's compound semiconductor, the second material comprises AlGaAs compound semi- conduct, the third and second etching treatment are performed by a reactive ion etching using an etchant gas comprising CC 1 2 F 2*
Claim 13
Dependent Claim
16 words
A method according to claim 1, wherein the sixth layer (32) is of an insulating material.
Claim 14
Dependent Claim
62 words
A method according to claim 12, wherein the tirst etching treatment (ii) comprises a selective etching of the fourth semiconductor layer (5) for exposing the portion of the third semiconductor layer (41) in the enhancement-mode transistor region, and another selective etching of the sixth insulating layer (32) for exposing the portion of the fifth semiconductor layer (6) in the depletion-mode transistor region.
Claim 15
Dependent Claim
17 words
A method according to claim 13, wherein said sixth insulating layer (32) is of Si0 2 .
Claim 16
Dependent Claim
103 words
A method according to claim 14 further comprising the steps of, after the formation step (f) of the sixth insulating layer (32), selectively forming another insulating layer (33) on the sixth insulating layer (32) in the depletion-mode transistor region, forming source electrodes and drain electrodes (35, 36, 37, 38) for the enhancement-mode and depletion-mode transistors, forming the masking layer (39) of a resist film with openings (40E, 40D) corresponding to gate electrodes (46, 47) of the transistors, and etching the sixth insulating layer (32) and the fifth semiconductor layer (6) through one opening (40E) in said masking layer in the enhancement-mode transistor region.
Claim 17
Dependent Claim
19 words
A method according to claim 15, wherein the other insulating layer (33) is of Si 3 N 4 .
Claim 18
Dependent Claim
34 words
A method according to claim 16, wherein the other insulating layer (33) is etched through the other opening (40D) in said masking layer (39), before the selective etching of the sixth insulating layer (32).
Claim 19
Dependent Claim
129 words
A method according to claim 14 further comprising the steps of, after the formation step (f) of the sixth insulating layer (32), decreasing the thickness of the sixth insulating layer (32) in the enhancement-mode transistor region by an etching, forming source electrodes and drain electrodes (35, 36, 37, 38) for the enhancement-mode and depletion-mode transistors through the sixth insulating layer (32), forming the masking layer (39) of a resist film with openings (40E, 40D) corresponding to gate electrodes (46, 47) of the transistors, etching the decreased sixth insulating layer (32) and the fifth semiconductor layer (6) through the openings (40E) in said masking layer in the enhancement-mode transistor region and a portion of the sixth insulating layer (32) in the depletion-mode transistor region to decrease the thickness thereof (32).
References Cited (Backward Citations)
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