Compound semiconductor device and method of producing it

Claim 1

A semiconductor device which includes an enhancement-mode transistor and a depletion-mode transistor, has a heterojunction, and uses a two-dimensional electron gas, comprising: a semi-insulating compound semiconductor substrate (10); a semiconductor channel layer (11) which is formed on the substrate (10) and in which the two-dimensional electron gas is generated; an electron-supply region including an electron supply layer (12) formed on the semiconductor channel layer (11) and forming the heterojunction (11A) with it; a first semiconductor layer (13) formed on the electron-supply region and having a composition different from the electron-supply layer (12); and gate electrodes (26, 27) of the enhancement-mode transistor and the depletion-mode transistor; characterised in that the semiconductor device also includes a second semiconductor layer (14) formed on the first semiconductor layer (13) and having a composition different from the first semiconductor layer (13), the gate electrode (27) of the depletion-mode transistor being located on the electron-supply region, and the gate electrode (26) of the enhancement-mode transistor being located in the electron-supply region at a depth from the base of the first semiconductor layer (13) corresponding to the thickness of the second semiconductor layer (14).

Claim 6

A method of producing a semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor, which has a heterojunction, and which uses a two-dimensional electron gas, comprising the steps of: forming a semiconductor channel layer (11) in which the two-dimensional electron gas is generated on a semi-insulating compound semiconductor substrate (10); forming an electron supply region including an electron-supply layer (12) on the semiconductor channel layer (11), the layers (11 and 12) forming the heterojunction; forming a first semiconductor layer (13) having a composition different from the electron-supply layer (12) on the electron supply region; selectively etching at least the semiconductor layer (13) to form grooves (24, 25) for the enhancement-mode transistor and for the depletion-mode transistor, respectively; and forming gate electrodes (26, 27) in the grooves; characterized in that a second semiconductor layer (14) having a composition different from the first semiconductor layer (13) is formed on the first semiconductor layer (13), in that a portion of the second semiconductor layer (14) corresponding to the gate region of the enhancement-mode transistor is selectively etched to form a recess (17); and in that in the etching step, the grooves (24, 25) are simultaneously etched by using an etchant which etches rapidly the first semiconductor layer (13) and etches slowly the second semiconductor layer (14) and the electron-supply layer (12) so that the exposed portion of the first semiconductor layer (13) and a portion of the electron-supply region having a thickness corresponding to the thickness of the second semiconductor layer (14) are etched to form the groove (24) for the gate electrode of the enhancement-mode transistor and a portion of the second semiconductor layer (14) and a portion of the first semiconductor layer (13) are etched to form the groove (25) for the depletion-mode transistor, to expose the electron-supply region.

Claim 7

A method of producing a semiconductor device which comprises an enhancement-mode transistor and a depletion-mode transistor, which has a heterojunction, and which uses a two-dimensional electron gas, comprising the steps of: forming a semiconductor channel layer (11) in which the two-dimensional electron gas is generated on a semi-insulating compound semiconductor substrate (10); forming an electron supply region including an electron-supply layer (12) on the semiconductor channel layer (11), the layers (11 and 12) forming the heterojunction; forming a first semiconductor layer (13) having a composition different from the electron-supply layer (12) on the electron supply region; selectively etching at least the semiconductor layer (13) to form grooves (24, 25) for the enhancement-mode transistor and for the depletion-mode transistor, respectively; and forming gate electrodes (26, 27) in the grooves; characterized in that a second semiconductor layer (14) having a composition different from the first semiconductor layer (13) is formed on the first semiconductor layer (13), in that a portion of the second semiconductor layer (14) corresponding to the gate region of the enhancement-mode transistor is selectively etched to form a recess (17); and in that in the etching step, the grooves (24, 25) are simultaneously etched by using an etchant which etches rapidly the first semiconductor layer (13) and etches slowly the second semiconductor layer (14) and the electron-supply layer (12) so that the exposed portion of the first semiconductor layer (13) and a portion of the electron-supply region having a thickness corresponding to the thickness of the second semiconductor layer (14) are etched to form the groove (24) for the gate electrode of the enhancement-mode transistor and a portion of the second semiconductor layer (14) and a portion of the first semiconductor layer (13) are etched to form the groove (25) for the depletion-mode transistor, to expose the electron-supply region.