EP0119089A2
Expired / Lapsed
EP
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GaAs semiconductor device and a method of manufacturing it
Assignee: Fujitsu Ltd
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Filing: 1984-03-12
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Granted: —
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Expires: 2004-03-12
Abstract
Abstract A method of manufacturing a GaAs semiconductor device of an enhancement/depletion, E/D, construction having a GaAs/AlGaAs heterojunction and using a two-dimensional electron gas, includes the steps of forming a heterojunction semiconductor substrate and etching a portion of the substrate to provide a gate portion of a depletion-mode FET DM. The substrate comprises a semi-insulating GaAs layer 1, an undoped GaAs layer 2, an N-type AlGaAs layer 4 forming an electron-supply layer, and a GaAs layer. The GaAs layer comprises a first GaAs layer 5, an etching stopping AlGaAs layer 6, and a second GaAs layer 7, with the first GaAs layer 5 being formed on the N-type GaAs layer 4. The etching step to provide the gate portion is preferably carried out by a dry etching method using an etchant of CCI 2 F 2 gas, so that the second GaAs layer 7 is etched but the AlGaAs layer 6 is not etched. Thus, the thickness of the layers between a gate electrode 19GD of the depletion-mode FET, DM and the GaAs 5 AlGaAs 4 hetero- junction plane is determined during the formation of the heterojunction substrate, so that a better uniformity of the threshold voltage of depletion-mode FET DM is obtained.
Inventors
- 👤 Shigeru Kuroda
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-10-26 17:41
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/80; H10D30/40; H10D30/47; H10D30/471; H10D30/475; H10D30/4755; H10D30/801; H10D84/00; H10D84/01; H10D84/02; H10D84/05; H10P; H10P50/00; H10P50/20; H10P50/24; H10P50/246; H10W; H10W10/00; H10W10/01; H10D84/80; H10D84/82; H10D84/83; H10D84/84; H10D84/86; Y; Y10; Y10S; Y10S438/00; Y10S438/97
Claims Analysis
Total Claims: 18
Claim 1
Independent Claim
214 words
A method of manufacturing a GaAs semiconductor device comprising an enhancement-mode GaAs FET (EM) having a heterojunction and using a two-dimensional electron gas and a depletion-mode GaAs FET(DM), comprising the steps of: forming an undoped GaAs layer (2) on a semi-insulating GaAs substrate (1); forming an N-type AlGaAs layer (4) above the undoped GaAs layer (2); forming a first GaAs layer (5) on the N-type AlGaAs layer (4); and, selectively etching the first GaAs layer (5) at the location of the gate of the enhancement-mode GaAs FET (EM); characterised by the formation of an AlGaAs layer (6) serving as an etching stopping layer on the first GaAs layer (5); forming a second GaAs layer (7) on the etching stopping AlGaAs layer (6); selectively etching the second GaAs layer (7), and the etching stopping AlGaAs layer (6), with part of the first GaAs layer (5) at the location of the gate of the enhancement-mode GaAs FET (EM); and, selectively etching the remainder of the first GaAs layer (5) at the location of the gate of the enhancement-mode GaAs FET (EM), and the second GaAs layer at a position for a gate of the depletion-mode GaAs FET (DM), this etching step being stopped by the N-type AlGaAs layer (4) and the etching stopping AlGaAs layer (6).
Claim 2
Independent Claim
214 words
A method of manufacturing a GaAs semiconductor device comprising an enhancement-mode GaAs FET (EM) having a heterojunction and using a two-dimensional electron gas and a depletion-mode GaAs FET(DM), comprising the steps of: forming an undoped GaAs layer (2) on a semi-insulating GaAs substrate (1); forming an N-type AlGaAs layer (4) above the undoped GaAs layer (2); forming a first GaAs layer (5) on the N-type AlGaAs layer (4); and, selectively etching the first GaAs layer (5) at the location of the gate of the enhancement-mode GaAs FET (EM); characterised by the formation of an AlGaAs layer (6) serving as an etching stopping layer on the first GaAs layer (5); forming a second GaAs layer (7) on the etching stopping AlGaAs layer (6); selectively etching the second GaAs layer (7), and the etching stopping AlGaAs layer (6), with part of the first GaAs layer (5) at the location of the gate of the enhancement-mode GaAs FET (EM); and, selectively etching the remainder of the first GaAs layer (5) at the location of the gate of the enhancement-mode GaAs FET (EM), and the second GaAs layer at a position for a gate of the depletion-mode GaAs FET (DM), this etching step being stopped by the N-type AlGaAs layer (4) and the etching stopping AlGaAs layer (6).
Claim 3
Dependent Claim
116 words
A method according to claim 1, in which the N-type AlGaAs layer (4) forms an electron-supply layer; the first GaAs layer (5) is N-type and forms an active layer of a depletion-mode GaAs MESFET (DM); the second GaAs layer (7) forms a contact layer; and, the selective etching of part of the first layer (5) leaves a thickness of the first GaAs layer (5) remaining similar to that of the second GaAs layer (7); and in which the method also includes the steps of: forming an isolation region (10,11) for the depletion-mode GaAs MESFET (DM); and, forming source (14SD, 14SE) and drain (14DD, 14DE) electrodes of both the GaAs FET's on the second GaAs layer (7).
Claim 4
Dependent Claim
42 words
A method according to claim 2, in which the depletion-mode GaAs FET (DM) has a heterojunction and uses a two-dimensional electron gas, in which the first GaAs layer (5) is formed on the AlGaAs layer (4) for the depletion-mode GaAs FET (DM).
Claim 5
Independent Claim
51 words
A method according to any one of the preceding claims, wherein the undoped GaAs layer (2), the N-type AlGaAs layer (4), the first GaAs layer (5), the etching stopping AlGaAs layer (6), and the second GaAs layer (7) are formed by molecular beam epitaxy or by metal organic chemical vapour deposition.
Claim 6
Independent Claim
28 words
A method according to any one of the preceding claims, in which the N-type AlGaAs layer (4) has a thickness in a range from 25 to 60 nm.
Claim 7
Independent Claim
29 words
A method according to any one of the preceding claims, in which the etching stopping AlGaAs layer (6) has a thickness in a range from 1 to 10 nm.
Claim 8
Dependent Claim
25 words
A method according to claim 6, in which the etching stopping AlGaAs layer (6) has a thickness in a range from 3 to 6 nm.
Claim 9
Independent Claim
27 words
A method according to any one of the preceding claims, in which the step of selectively etching the GaAs is carried out by a dry etching method.
Claim 10
Dependent Claim
29 words
A method according to claim 8, in which the dry etching method is a reactive ion etching method using an etchant comprising chlorine system gas and fluorine system gas.
Claim 11
Dependent Claim
18 words
A method according to claim 9, in which the etchant gas comprises CC 1 2 F 2 .
Claim 12
Independent Claim
39 words
A method according to any one of the preceding claims, which also includes the step of forming an undoped AlGaAs layer (3) on the undoped GaAs layer (2), prior to the step of forming the N-type AlGaAs layer (4).
Claim 13
Independent Claim
40 words
A method according to any one of the preceding claims, which also includes the step of forming source (14SE, 14SD) and drain (14DE, 14DD) electrodes on the second GaAs layer (7), prior to the step of selectively etching the GaAs.
Claim 14
Independent Claim
35 words
A method according to any one of the preceding claims, which also includes the step of forming gate electrodes (19GE, 19GD) on the N-type AlGaAs layer (4) and the AlGaAs etching stopping layer (7), respectively.
Claim 15
Dependent Claim
153 words
A GaAs semiconductor device comprising an enhancement-mode FET (EM) and a depletion-mode FET (DM) which both have a heterojunction and use a two-dimensional electron gas, comprising: an undoped GaAs layer (2) on a semi-insulating GaAs substrate (1); an N-type AlGaAs layer (4) formed above the undoped GaAs layer (2) ; a gate electrode (19GE) of the enhancement-mode FET (EM) formed on a portion of the N-type AlGaAs layer (4); and, a first GaAs layer (5) formed on the N-type AlGaAs layer (4); characterised in that it also comprises: an etching stopping AlGaAs layer (6) formed on the first GaAs layer (5); a gate electrode (19GD) of the depletion-mode FET (DM) formed on a portion of the etching stopping AlGaAs layer (6); a second GaAs layer (7) formed on the etching stopping AlGaAs layer (6); and, source electrodes (14SE, 14SD) and drain (14DE,14DD) electrodes having alloyed regions extending to the undoped GaAs layer (2).
Claim 16
Dependent Claim
153 words
A GaAs semiconductor device comprising an enhancement-mode FET (EM) and a depletion-mode FET (DM) which both have a heterojunction and use a two-dimensional electron gas, comprising: an undoped GaAs layer (2) on a semi-insulating GaAs substrate (1); an N-type AlGaAs layer (4) formed above the undoped GaAs layer (2) ; a gate electrode (19GE) of the enhancement-mode FET (EM) formed on a portion of the N-type AlGaAs layer (4); and, a first GaAs layer (5) formed on the N-type AlGaAs layer (4); characterised in that it also comprises: an etching stopping AlGaAs layer (6) formed on the first GaAs layer (5); a gate electrode (19GD) of the depletion-mode FET (DM) formed on a portion of the etching stopping AlGaAs layer (6); a second GaAs layer (7) formed on the etching stopping AlGaAs layer (6); and, source electrodes (14SE, 14SD) and drain (14DE,14DD) electrodes having alloyed regions extending to the undoped GaAs layer (2).
Claim 17
Dependent Claim
31 words
A device according to claim 14, in which the drain electrode (74A Figure 15) of the enhancement-mode FET (EM) and the source electrode (74A) of the depletion-mode FET (DM) are common.
Claim 18
Dependent Claim
27 words
A device according to claim 14, in which all the electrodes (14SE, 14DE, 14SD, 14DD, 19GE and 19 GD) of both FET's are separate from one another.
References Cited (Backward Citations)
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