EP0264932A1
Expired / Lapsed
EP
⏱️ 0.0 years remaining
Field effect transistor
Assignee: Sumitomo Electric Industries Ltd
•
Filing: 1987-10-21
•
Granted: —
•
Expires: 2007-10-21
Abstract
Abstract A field effect transistor comprises an InP substrate, an n-tupe semiconductor layer formed on the InP substrate, a GaInAs layer formed on the n-type semiconductor layer, no impurities being added to the GaInAs layer, an AlInAs layer formed on the GaInAs layer, a control electrode provided on the AlInAs layer, and a source electrode and a drain electrode provided at both the sides of the control electrode so as to make an ohmic contact to the GaInAs layer.
Inventors
- 👤 Goro c/o Yokohama Works of Sumito Sasaki
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-01 16:55
CPC Classifications
H; H10; H10D; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D64/00; H10D64/60; H10D64/602
Claims Analysis
Total Claims: 9
Claim 1
Independent Claim
78 words
A field effect transistor, comprising: an InP substrate; an n-type semiconductor layer formed on said InP substrate; a GaInAs layer formed on said n-type semiconductor layer, no impurities being added to said GaInAs layer; an AlInAs layer formed on said GaInAs layer; a control electrode provided on said AlInAs layer; and a source electrode and a drain electrode provided at both the sides of said control electrode so at to make an ohmic contact to said GaInAs layer.
Claim 2
Dependent Claim
78 words
A field effect transistor, comprising: an InP substrate; an n-type semiconductor layer formed on said InP substrate; a GaInAs layer formed on said n-type semiconductor layer, no impurities being added to said GaInAs layer; an AlInAs layer formed on said GaInAs layer; a control electrode provided on said AlInAs layer; and a source electrode and a drain electrode provided at both the sides of said control electrode so at to make an ohmic contact to said GaInAs layer.
Claim 3
Dependent Claim
18 words
A field effect transistor as claimed in claim 1, wherein said n-type semiconductor layer is an AlInAs layer.
Claim 4
Dependent Claim
17 words
A field effect transistor as claimed in claim 1, wherein said n-type semiconductor is an Inp layer.
Claim 5
Dependent Claim
19 words
A field effect transistor as claimed in claim 1, wherein no impuritie s are added to said AlInAs layer.
Claim 6
Dependent Claim
21 words
A field effect transistor as claimed in claim 1, wherein the electrical conduction of said AlInAs layer is of a p-type.
Claim 7
Dependent Claim
21 words
A field effect transistor as claimed in claim 1, wherein the electrical conduction of said AlInAs layer is of an n-type.
Claim 8
Dependent Claim
19 words
A field effect transistor as claimed in claim 1, wherein said GaInAs layer has a thickness of 150 -1000Å.
Claim 9
Dependent Claim
35 words
A field effect transistor as claimed in claim 1, wherein said n-type semiconductor layer includes impurities having the concentration of 1x 10¹⁷ - 5 x 10¹⁸ cm⁻³ and has a thickness of 500 - 2000Å.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
Maintenance schedule is calculated for granted US utility patents.