Patent US4931833A successfully refreshed from Google Patents.
EP0147196A2
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EP
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A semiconductor member and semiconductor device employing such a member
Assignee: Hitachi Ltd
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Filing: 1984-12-20
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Granted: —
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Expires: 2004-12-20
Abstract
Abstract A semiconductor member has a structure wherein a first semiconductor layer (31) is located between second and third semiconductor layers (32, 33) which have forbidden band widths greater than a forbidden band width of the first semiconductor layer (31). The second semiconductor layer (33) is between the first semiconductor layer (71) and a substrate and is doped with impurities. The semiconductor member constructs a depletion type device with the first and second semiconductor layers (31, 33), and an enhancement type device with the first and third semiconductor layers (31, 32). A semiconductor device can be formed as an enhancement or depletion type by selectively connecting the semiconductor layers (31, 32, 33).
Inventors
- 👤 Yasushi Sawada
- 👤 Kiichi Ueyanagi
- 👤 Yoshifumi Katayama
- 👤 Yasuhiro Shiraki
- 👤 Makoto Morioka
- 👤 Takao Kuroda
- 👤 Tomoyoshi Mishima
Bibliographic Details
Application Number
—
Jurisdiction
EP
Data Source
google_patents
Last Synchronized
2026-11-02 01:44
CPC Classifications
H; H10; H10D; H10D48/00; H10D48/30; H10D48/32; H10D48/36; H10D30/00; H10D30/40; H10D30/47; H10D30/471; H10D30/473; H10D30/4732; H10D30/60; H10D30/67; H10D30/6729; H10D30/6737; H10D30/6738; H10D30/674; H10D30/675; H10D62/00; H10D62/80; H10D62/85; H10D62/852; H10D64/00; H10D64/60; H10D64/602; H10D64/64; H10D84/00; H10D84/01; H10D84/0123; H10D84/0126; H10D84/0163; H10D84/02; H10D84/05; H10D84/80; H10D84/86; H10D62/854
Claims Analysis
Total Claims: 11
Claim 1
Independent Claim
87 words
A semiconductor member having a first semiconductor layer (31, 45) which is undoped, a second semiconductor layer (33, 43) which has a forbidden band width greater than that of the first semiconductor layer (31, 45) and which is doped with impurities, and a third semiconductor layer (32, 45) which has a forbidden band width greater than that of the first semiconductor layer and which is undoped, the first semiconductor layer (31, 45) being between the second semiconductor layer (33, 43) and the third semiconductor layer (32, 46).
Claim 2
Dependent Claim
87 words
A semiconductor member having a first semiconductor layer (31, 45) which is undoped, a second semiconductor layer (33, 43) which has a forbidden band width greater than that of the first semiconductor layer (31, 45) and which is doped with impurities, and a third semiconductor layer (32, 45) which has a forbidden band width greater than that of the first semiconductor layer and which is undoped, the first semiconductor layer (31, 45) being between the second semiconductor layer (33, 43) and the third semiconductor layer (32, 46).
Claim 3
Dependent Claim
18 words
A semiconductor member according to claim 1 having an oxidation-proof semiconductor layer (46) on the third semiconductor layer.
Claim 4
Dependent Claim
47 words
A semiconductor member according to claim 1 or claim 2 having a semiconductor layer (44) of the same material as that of said second semiconductor layer (43) but which is undoped, and which is interposed between the first semiconductor layer (45) and the second semiconductor layer (43).
Claim 5
Dependent Claim
30 words
A semiconductor member according to any one of claims 1 to 3 wherein the second semiconductor layer (46) is between the first semiconductor layer (45) and a semiconductor substrate (40).
Claim 6
Dependent Claim
27 words
A semiconductor member according to claim 4, having at least one undoped semiconductor layer (41, 42) interposed between the second semiconductor layer (43) and the substrate (40).
Claim 7
Dependent Claim
40 words
A semiconductor member according to claim 5, wherein the undoped semiconductor layer (41, 42) between the second semiconductor layer (43) and the substrate (40) is of the same material as that of the substrate (40) or the second semiconductor.layer (43).
Claim 8
Dependent Claim
55 words
A semiconductor member according to claim 5 having a semiconductor layer (41) of the same material as that of the substrate (40) and a semiconductor layer (42) of the same material as that of the second semiconductor layer (43) interposed between the substrate (40) and the second semiconductor layer (43) successively from the substrate side.
Claim 9
Dependent Claim
119 words
A semiconductor device having: a semiconductor member according to any one of the preceding claims; at least one control electrode for controlling currents flowing within the first semiconductor layer adjacent the interfaces of the first semiconductor layer with the second and third semiconductor layers respectively, the at least one control electrode being on a side of the second or third semiconductor layers remote from the first semiconductor layer; and at least one pair of ohmic electrodes having electrode regions extending from the third semiconductor layer to the interface between the first semiconductor layer and the second or third semiconductor layer, the at least one pair of ohmic electrodes being on either side of the at least one control electrode.
Claim 10
Dependent Claim
63 words
A semiconductor device according to claim 8 having one pair of ohmic electrodes with electrode regions extending from the third semiconductor layer to the interface between the first semiconductor layer and the second semiconductor layer, and another pair of ohmic electrodes with electrode regions extending from the third semiconductor layer to the interface between the first semiconductor layer and the third semiconductor layer.
Claim 11
Dependent Claim
84 words
A semiconductor device according to claim 8 or claim 9, having one control electrode on a side of the second semiconductor layer remote from the first semiconductor layer for controlling currents flowing within the first semiconductor layer adjacent the interface of the first and second semiconductor layers, and one control electrode on a side of the third semiconductor layer remote from the first semiconductor layer for controlling currents flowing within the first semiconductor layer adjacent the interface of the first and third semiconductor layers.
References Cited (Backward Citations)
No citation records indexed.
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