External expansion bus interface

Claim 1

An apparatus comprising: a central processing unit, a bus interface for selecting and deselecting one or more expansion devices, an internal bus coupling the bus interface to the central processing unit, and an expansion bus coupling the bus interface to the expansion devices, the bus interface including at least one internal buffer coupled to the internal bus for buffering signals to and from the internal bus, a connector coupled to the internal buffers for attaching and removing the expansion bus, at least one expansion buffer coupled to the connector and to the expansion bus for buffering signals to and from the expansion bus, and control logic means responsive to signals received from said central processing unit across said internal bus and through said internal buffer, said connector and said expansion buffer for enabling and disabling the internal or expansion buffers so coupled, whereby the expansion devices are also enabled and disabled.

Claim 2

An apparatus comprising: a central processing unit, a bus interface for selecting and deselecting one or more expansion devices, an internal bus coupling the bus interface to the central processing unit, and an expansion bus coupling the bus interface to the expansion devices, the bus interface including at least one internal buffer coupled to the internal bus for buffering signals to and from the internal bus, a connector coupled to the internal buffers for attaching and removing the expansion bus, at least one expansion buffer coupled to the connector and to the expansion bus for buffering signals to and from the expansion bus, and control logic means responsive to signals received from said central processing unit across said internal bus and through said internal buffer, said connector and said expansion buffer for enabling and disabling the internal or expansion buffers so coupled, whereby the expansion devices are also enabled and disabled.

Claim 7

A method of enabling and disabling communication between a central processing unit and each of a plurality of devices coupled through buffer means to a bus which in turn is coupled to the central processing unit, each said device having a respective address, and said buffer means including an address buffer and a data buffer, said method comprising the steps of: storing in a storage arrangement for each said device an indication of whether communication for that device is to be enabled for said address thereof; transferring an address from the central processing unit to the address buffer; reading the address from the address buffer; disabling the data buffer when the address buffer contains the address of one of said devices for which the storage arrangement contains an indication that communication is to be disabled; and enabling the data buffer when the address buffer contains the address of one of said devices for which the storage arrangement contains an indication that communication is to be enabled.

Claim 8

A method of enabling and disabling communication between a central processing unit and each of a plurality of devices coupled through buffer means to a bus which in turn is coupled to the central processing unit, each said device having a respective address, and said buffer means including an address buffer and a data buffer, said method comprising the steps of: storing in a storage arrangement for each said device an indication of whether communication for that device is to be enabled for said address thereof; transferring an address from the central processing unit to the address buffer; reading the address from the address buffer; disabling the data buffer when the address buffer contains the address of one of said devices for which the storage arrangement contains an indication that communication is to be disabled; and enabling the data buffer when the address buffer contains the address of one of said devices for which the storage arrangement contains an indication that communication is to be enabled.

Claim 9

A method of communicating between first and second devices via a data path between the devices and a computer bus between the devices which includes a plurality of address lines, a plurality of data lines, a read signal line, and a write signal line without causing contention with other devices regardless of their addresses, said method comprising the steps of: sending a first signal from said first device to said second device on the data path that noncontending communications are beginnings; sending a read signal from said first device to said second device on the read signal line while sending an address on the address lines whereby the address can be interpreted as an instruction or data; and sending a second signal from said first device to said second device on the data path, to indicate that normal communications are resuming.

Claim 10

A method of communicating between first and second devices via a data path between the devices and a computer bus between the devices which includes a plurality of address lines, a plurality of data lines, a read signal line, and a write signal line without causing contention with other devices regardless of their addresses, said method comprising the steps of: sending a first signal from said first device to said second device on the data path that noncontending communications are beginnings; sending a read signal from said first device to said second device on the read signal line while sending an address on the address lines whereby the address can be interpreted as an instruction or data; and sending a second signal from said first device to said second device on the data path, to indicate that normal communications are resuming.

Claim 13

A method of detecting a central processing unit through a bus interface, the bus interface being coupled by an internal bus to the central processing unit and by an expansion bus to one or more expansion devices, comprising the steps of: selecting a line of the expansion bus which is normally driven by the central processing unit in a predetermined manner through the internal bus and the bus interface, testing for the selected line of the expansion bus being driven in said predetermined manner in which the central processing unit would drive the line, and testing for the selected line being driven in a manner which is different from said predetermined manner in which the central processing unit would drive the line and which is a manner in which a device other than said central processing unit would drive the selected line.

Claim 14

A method of detecting a central processing unit through a bus interface, the bus interface being coupled by an internal bus to the central processing unit and by an expansion bus to one or more expansion devices, comprising the steps of: selecting a line of the expansion bus which is normally driven by the central processing unit in a predetermined manner through the internal bus and the bus interface, testing for the selected line of the expansion bus being driven in said predetermined manner in which the central processing unit would drive the line, and testing for the selected line being driven in a manner which is different from said predetermined manner in which the central processing unit would drive the line and which is a manner in which a device other than said central processing unit would drive the selected line.

Claim 15

An apparatus, comprising: a processor; an internal bus coupled to said processor; external device means; an external bus coupled to said external device means; selectively actuable buffer means for respectively permitting and preventing information transfer between said internal bus and external bus when respectively enabled and disabled; memory means for storing information defining for a specified address whether said external device means is to be prevented from responding to said specified address; control means responsive to receipt of said specified address from said processor across said internal bus for disabling said buffer means when said information in said memory means indicates said external device means is to be prevented from responding to said address; and means responsive to said processor for enabling and disabling a predetermined mode of operation, said control means being responsive to said predetermined mode of operation for loading into said memory means information sent by said processor across said internal bus and for preventing said external device means from responding to any address sent by said processor across said internal bus.

Claim 16

An apparatus, comprising: a processor; an internal bus coupled to said processor; external device means; an external bus coupled to said external device means; selectively actuable buffer means for respectively permitting and preventing information transfer between said internal bus and external bus when respectively enabled and disabled; memory means for storing information defining for a specified address whether said external device means is to be prevented from responding to said specified address; control means responsive to receipt of said specified address from said processor across said internal bus for disabling said buffer means when said information in said memory means indicates said external device means is to be prevented from responding to said address; and means responsive to said processor for enabling and disabling a predetermined mode of operation, said control means being responsive to said predetermined mode of operation for loading into said memory means information sent by said processor across said internal bus and for preventing said external device means from responding to any address sent by said processor across said internal bus.