Bus activity sequence controller

Claim 2

In a data processing system comprising a main memory and a CPU coupled to a system bus, and a peripheral sequence controller for accessing adapters coupled to respective peripheral devices, the peripheral sequence controller being coupled to the system bus and comprising: a microprocessor; a plurality of adapter ports, each for communicating with an adapter; logic means for polling each adapter port to determine if an adapter having peripheral devices is connected to the adapter port; a plurality of direct memory access means each for controlling a respective direct memory access to and from said main memory and to and from one of said peripheral devices through one of the adapter ports; and a sequencer means for sequentially enabling selected direct memory access means to have access to respective adapter ports for DMA data transfers between main memory and peripheral devices coupled to the adapter ports and for enabling the microprocessor access to the adapter ports to service interrupts after each direct memory access.

Claim 3

A sequence controller for accessing peripheral devices as claimed in claim 1 further comprising means for restricting the amount of data transferred to or from each adapter port during each direct memory access.

Claim 4

A sequence controller for accessing peripheral devices as claimed in claim 1 wherein the sequencer means comprises: a counter; a decoder in communication with the counter for separating each count into separate events; a first logic means for polling each adapter port and the microprocessor for request signals to determine if data is to be transferred to or from each adapter; and a second logic means which combines the request signals from each of the adapter ports and the microprocessor with one of the separate events for alternating access between each adapter port and the microprocessor.

Claim 5

A sequence controller for accessing peripheral devices as claimed in claim 3 wherein a count of the counter generates an event that is combined with the request signal from the microprocessor for gaining access to the global bus.

Claim 6

In a computer system having a plurality of peripheral devices, a main memory, a system bus, a CPU, a sequence controller for accessing peripheral devices, the sequence controller comprising: a microprocessor; adapter ports for communicating with the peripheral devices; direct memory access means for controlling direct memory accesses to and from main memory and to and from peripheral devices, the direct memory access means having one channel for each adapter port; a global bus in communication with the microprocessor and each said channel for allowing communication with the computer system; and an alternating sequence operation means for allocating successive time periods to each of the channels and the microprocessor in turn for controlling access to the global bus, wherein the alternating sequence operation means comprises: a counter for generating successive counts; a decoder in communication with the counter for separating successive counts into separate events; a first logic means for polling each adapter port and the microprocessor for request signals to determine if data is to be transferred to or from each adapter; and a second logic means which combines the request signals from each of the adapter ports and the microprocessor with each of the events for alternating access to the global bus.

Claim 7

In a computer system having a plurality of peripheral devices, a main memory, a system bus, a CPU, a sequence controller for accessing peripheral devices, the sequence controller comprising: a microprocessor; adapter ports for communicating with the peripheral devices; direct memory access means for controlling direct memory accesses to and from main memory and to and from peripheral devices, the direct memory access means having one channel for each adapter port; a global bus in communication with the microprocessor and each said channel for allowing communication with the computer system; and an alternating sequence operation means for allocating successive time periods to each of the channels and the microprocessor in turn for controlling access to the global bus, wherein the alternating sequence operation means comprises: a counter for generating successive counts; a decoder in communication with the counter for separating successive counts into separate events; a first logic means for polling each adapter port and the microprocessor for request signals to determine if data is to be transferred to or from each adapter; and a second logic means which combines the request signals from each of the adapter ports and the microprocessor with each of the events for alternating access to the global bus.

Claim 8

A sequence controller for accessing peripheral devices as claimed in claim 5 further comprising logic means for determining which adapter port has an adapter with peripheral devices connected to it for limiting the alternating sequence operation means between channels to each adapter port having an adapter wit at least one peripheral device connected to it and the microprocessor.

Claim 9

A sequence controller for accessing peripheral devices as claimed in claim 5 further comprising logic means for determining that there is only one adapter having a peripheral devices coupled to it and limiting the sequence to that adapter and the microprocessor.

Claim 10

A sequence controller for accessing peripheral devices as claimed in claim 5 further comprising means for restricting the amount of data transferred per time period a predetermined number of bytes of data to or from each adapter port.

Claim 11

A sequence controller for accessing peripheral devices as claimed in claim 5 wherein a count of the counter generates an event that is combined with the request signal from the microprocessor for gaining access to the global bus.

Claim 12

In a data processing system comprising a main memory and a CPU coupled to a system bus, and a peripheral controller for accessing peripheral devices, the peripheral controller being coupled to the system bus and comprising: a plurality of adapter ports, each for communicating with a peripheral device; a plurality of direct memory access (DMA) means each for controlling transfers of data in direct memory accesses through one of the adapter ports to and from main memory and to and from a peripheral device; a microprocessor for establishing DMA data paths by transferring to the DMA means address parameters for a DMA transfer; and a sequencer means for sequentially enabling selected direct memory access means to have access to respective adapter ports for DMA data transfers between main memory and peripheral devices coupled to the adapter ports and for enabling the microprocessor access to the adapter ports to service interrupts after each direct memory access.

Claim 13

In a data processing system comprising a main memory and a CPU coupled to a system bus, and a peripheral controller for accessing peripheral devices, the peripheral controller being coupled to the system bus and comprising: a plurality of adapter ports, each for communicating with a peripheral device; a plurality of direct memory access (DMA) means each for controlling transfers of data in direct memory accesses through one of the adapter ports to and from main memory and to and from a peripheral device; a microprocessor for establishing DMA data paths by transferring to the DMA means address parameters for a DMA transfer; and a sequencer means for sequentially enabling selected direct memory access means to have access to respective adapter ports for DMA data transfers between main memory and peripheral devices coupled to the adapter ports and for enabling the microprocessor access to the adapter ports to service interrupts after each direct memory access.

Claim 14

A controller for accessing peripheral devices as claimed in claim 10 further comprising means for restricting the amount of data transferred to or from each adapter port during each direct memory access.

Claim 15

A controller as claimed in claim 11 further comprising an adapter coupled to each port to buffer data to be transferred by each DMA means.

Claim 16

A controller as claimed in claim 10 further comprising means for limiting an enabling sequence of the sequencer means where a peripheral device is not coupled to a port.