Well-logging data processing system having segmented serial processor-to-peripheral data links

Claim 2

A data processing system including peripheral units connected thereto, said system comprising: (a) a central processor unit including a main memory; (b) a plurality of serial link units, each having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each serial channel sending on transmit lines and receiving on receive lines serial data to and from a first plurality of the peripheral units; (c) a processor interface unit responsive to data ready signals from said processor unit and said serial link units, for controlling the transfer of data between said central processor unit and said plurality of serial link units, said interface unit including an internal interface bus; and (d) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit, said plurality of serial link units enabling the simultaneous input/output transfer of data to a plurality of the peripherals in said first plurality of peripherals.

Claim 3

The processing system of claim 1 further including: (a) a processor bus interconnecting a second plurality of the peripherals units to said central processor unit for data transfers therebetween, said processor bus connecting said processor interface unit to said central processor; and (b) a system bus interconnecting said microprocessor unit, said processor interface unit and said plurality of serial link units for data transfers therebetween, said buses enabling the transfer of data to occur simultaneously over established data links between (i) said processor unit and a peripheral in said second plurality of peripherals, (ii) said processor unit and said interface unit, (iii) said interface unit and said microprocessor unit. (iv) said interface unit and one of said plurality of serial units, (v) said microprocessor and one of said plurality of serial units, and (vi) each of said plurality of serial link units and any one of the peripherals in said first plurality of peripherals connected to the plurality of serial input/output channels of said serial link unit.

Claim 4

The processing system of claim 1 wherein said processor interface unit includes: (a) a plurality of interface data registers connected to said processor bus for temporarily storing information being passed between said processor unit and said microprocessor unit or said plurality of serial link units; (b) a direct memory access unit responsive to said microprocessor unit for transferring data between said interface data registers and said serial link units; and (c) means responsive to said microprocessor unit for transferring data between said interface data registers and said main memory, said transferring means and said direct memory access unit responding to initiating signals from said microprocessor unit to enable data comprising outgoing message data to be transferred from main memory to a serial link unit and vice versa.

Claim 5

The processing system of claim 3 wherein said transferring means obtains data from said main memory independently of processor control.

Claim 6

The processing system of claims 1, 2 or 3 wherein each said serial link unit comprises: (a) a message buffer memory connected to said serial link bus for temporarily storing incoming and outgoing message data for a peripheral connected to said serial link unit; (b) a receive direct memory access unit connected to said serial link bus for controlling the transfer of data between the receive lines of said plurality of serial input/output channels and said buffer memory; (c) a transmit direct memory access unit connected to said serial link bus for controlling the transfer of data between the transmit lines of said plurality of serial input/output channels and said buffer memory; and (d) a plurality of serial controllers each connected to said serial link bus and each associated with one of said plurality of serial input/output channels, each said controller supervising the exchange of data between the peripheral connected to the serial channel and said serial link unit.

Claim 7

The processing system of claim 5 further including a baud rate generator connected to said serial link bus for generating timing signals to determine the transmission rate of the serial data to said peripherals connected to said serial link unit.

Claim 8

The processing system of claim 5 wherein said transmit and said receive direct memory access units each comprise a plurality of direct memory access channels, one for each of said plurality of serial input/output channels of said serial link unit.

Claim 9

The processing system of claim 7 further including a bus arbitration unit for resolving access to said serial link bus between said direct memory access units and any data transfer to said serial link unit from said microprocessor unit or said processor interface unit.

Claim 10

The processing system of claim 8 wherein said direct memory access units alternate in priority as between themselves as to which said access unit will obtain control of said serial link bus as determined by said bus arbitration unit, said plurality of direct memory access channels in each said access unit having a rotating priority therebetween where the channel last serviced has the lowest priority.

Claim 11

A data processing system including peripheral units connected thereto, said system comprising: (a) a central processor unit including a main memory; (b) a plurality of serial link units, each having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each serial channel sending on transmit lines and receiving on receive lines serial data to and from said peripheral units; (c) a processor interface unit responsive to data ready signals from said processor unit and said serial link units, for controlling the transfer of data between said central processor unit and said plurality of serial link units, said interface unit including an internal interface bus; and (d) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit, said plurality of serial link units enabling the simultaneous input/output transfer of data to a plurality of said peripherals.

Claim 12

A data processing system including peripheral units connected thereto, said system comprising: (a) a central processor unit including a main memory; (b) a plurality of serial link units, each having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each serial channel sending on transmit lines and receiving on receive lines serial data to and from said peripheral units; (c) a processor interface unit responsive to data ready signals from said processor unit and said serial link units, for controlling the transfer of data between said central processor unit and said plurality of serial link units, said interface unit including an internal interface bus; and (d) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit, said plurality of serial link units enabling the simultaneous input/output transfer of data to a plurality of said peripherals.

Claim 13

The processing system of claim 10 further including a system bus interconnecting said microprocessor unit, said processor interface unit, and said plurality of serial link units, for data transfers therebetween, said buses enabling the transfer of data to occur simultaneously over established data links between (i) said processor unit and said interface unit, (ii) said interface unit and said microprocessor unit, (iii) said interface unit and one of said plurality of serial units, (iv) said microprocessor and one of said plurality of serial units, and (v) each of said plurality of serial link units and any one of said peripherals connected to the plurality of serial input/output channels of said serial link unit.

Claim 14

The processing system of claim 10 wherein said processor interface unit includes: (a) a plurality of interface data registers connected to said processor bus for temporarily storing information being passed between said processor unit and said microprocessor unit or said plurality of serial link units; (b) a direct memory access unit responsive to said microprocessor unit for transferring data between said interface data registers and said serial link units; and (c) means responsive to said microprocessor unit for transferring data between said interface data registers and said main memory, said transferring means and said direct memory access unit responding to initiating signals from said microprocessor unit to enable data comprising outgoing message data to be transferred from main memory to a serial link unit and vice versa.

Claim 15

The processing system of claim 12 wherein said transferring means obtains data from said main memory independently of processor control.

Claim 16

The processing system of claims 10, 11 or 12 wherein each said serial link unit comprises: (a) a message buffer memory connected to said serial link bus for temporarily storing incoming and outgoing message data for a peripheral connected to said serial link unit; (b) a receive direct memory access unit connected to said serial link bus for controlling the transfer of data between the receive lines of said plurality of serial input/output channels and said buffer memory; (c) a transmit direct memory access unit connected to said serial link bus for controlling the transfer of data between the transmit lines of said plurality of serial input/output channels and said buffer memory; and (d) a plurality of serial controllers each connected to said serial link bus and each associated with one of said plurality of serial input/output channels, each said controller supervising the exchange of data between the peripheral connected to the serial channel and said serial link unit.

Claim 17

The processing system of claim 14 further including a baud rate generator connected to said serial link bus for generating timing signals to determine the transmission rate of the serial data to said peripherals connected to said serial link unit.

Claim 18

The processing system of claim 14 wherein said transmit and said receive direct memory access units each comprise a plurality of direct memory access channels, one for each of said plurality of serial input/output channels of said serial link unit.

Claim 19

The processing system of claim 16 further including a bus arbitration unit for resolving access to said serial link bus between said direct memory access units and any data transfer to said serial link unit from said microprocessor unit or said processor interface unit.

Claim 20

The processing system of claim 17 wherein said direct memory access units alternate in priority as between themselves as to which said access unit will obtain control of said serial link bus as determined by said bus arbitration unit, said plurality of direct memory access channels in each said access unit having a rotating priority therebetween where the channel last serviced has the lowest priority.

Claim 21

A well-logging data acquisition and processing system responsive to signals from well-logging tools contained in a well borehole drilled into the earth's formations, for obtaining well-site measurements from the tools and for generating output logs of well parameters determined from the measurements, the system having a plurality of peripherals units which include a logging tool interface unit, the system comprising: (a) first and second parallel central processors, each including a main memory unit for storing program routines and for storing data comprising messages to and from a first plurality of peripheral units, each said processor including (i) a plurality of serial link units, each having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each serial channel sending on transmit lines and receiving on receive lines serial data to and from said first plurality of the peripheral units, (ii) a processor interface unit responsive to data ready signals, for controlling the transfer of data between the central processor unit and said plurality of serial link units, said interface unit including an internal interface bus, (iii) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit, said plurality of serial link units enabling the simultaneous input/output transfer of data to a plurality of the peripherals in said first plurality of peripherals, and (iv) a processor bus for data transfer between said central processor unit, its main memory, said processor interface unit, and a second plurality of said peripheral units; and (b) a switch means connected to said processor buses and the transmit and receive lines from each channel of each of said serial link units and responsive to a switch command for controlling which of said first or second processor units is connected to said peripherals for data transfers therebetween.

Claim 22

A well-logging data acquisition and processing system responsive to signals from well-logging tools contained in a well borehole drilled into the earth's formations, for obtaining well-site measurements from the tools and for generating output logs of well parameters determined from the measurements, the system having a plurality of peripherals units which include a logging tool interface unit, the system comprising: (a) first and second parallel central processors, each including a main memory unit for storing program routines and for storing data comprising messages to and from a first plurality of peripheral units, each said processor including (i) a plurality of serial link units, each having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each serial channel sending on transmit lines and receiving on receive lines serial data to and from said first plurality of the peripheral units, (ii) a processor interface unit responsive to data ready signals, for controlling the transfer of data between the central processor unit and said plurality of serial link units, said interface unit including an internal interface bus, (iii) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit, said plurality of serial link units enabling the simultaneous input/output transfer of data to a plurality of the peripherals in said first plurality of peripherals, and (iv) a processor bus for data transfer between said central processor unit, its main memory, said processor interface unit, and a second plurality of said peripheral units; and (b) a switch means connected to said processor buses and the transmit and receive lines from each channel of each of said serial link units and responsive to a switch command for controlling which of said first or second processor units is connected to said peripherals for data transfers therebetween.

Claim 23

The processing system of claim 19 wherein each said central processing unit includes a system bus interconnecting said microprocessor unit, said processor interface unit and said plurality of serial link units for data transfers therebetween, said buses enabling the transfer of data to occur simultaneously over established data links between (i) said processor unit and said interface unit, (ii) said interface unit and said microprocessor unit, (iii) said interface unit and one of said plurality of serial units, (iv) said microprocessor and one of said plurality of serial units, and (v) each of said plurality of serial link units and any one of said peripherals in said first plurality of peripherals connected to the plurality of serial input/output channels of said serial link unit.

Claim 24

The processing system of claim 19 wherein said processor interface unit includes: (a) a plurality of interface data registers connected to said processor bus for temporarily storing information being passed between said processor unit and said microprocessor unit or said plurality of serial link units; (b) a direct memory access unit responsive to said microprocessor unit for transferring data between said interface data registers and said serial link units; and (c) means responsive to said microprocessor unit for transferring data between said interface data registers and said main memory, said transferring means and said direct memory access unit responding to initiating signals from said microprocessor unit to enable data comprising outgoing message data to be transferred from main memory to a serial link unit, and vice versa.

Claim 25

The processing system of claim 21 wherein said transferring means obtains data from said main memory independently of processor control.

Claim 26

The processing system of claims 19, 20 or 21 wherein each said serial link unit comprises: (a) a message buffer memory connected to said serial link bus for temporarily storing incoming and outgoing message data for a peripheral connected to said serial link unit; (b) a receive direct memory access unit connected to said serial link bus for controlling the transfer of data between the receive lines of said plurality of serial input/output channels and said buffer memory; (c) a transmit direct memory access unit connected to said serial link bus for controlling the transfer of data between the transmit lines of said plurality of serial input/output channels and said buffer memory; and (d) a plurality of serial controllers each connected to said serial link bus and each associated with one of said plurality of serial input/output channels, each said controller supervising the exchange of data between the peripheral connected to the serial channel and said serial link unit.

Claim 27

The processing system of claim 23 further including a baud rate generator connected to said serial link bus for generating timing signals to determine the transmission rate of the serial data to said peripherals connected to said serial link unit.

Claim 28

The processing system of claim 23 wherein said transmit and said receive direct memory access units each comprise a plurality of direct memory access channels, one for each of said plurality of serial input/output channels of said serial link unit.

Claim 29

The processing system of claim 25 further including a bus arbitration unit for resolving access to said serial link bus between said direct memory access units and any data transfer to said serial link unit from said microprocessor unit or said processor interface unit.

Claim 30

The processing system of claim 26 wherein said direct memory access units alternate in priority as between themselves as to which said access unit will obtain control of said serial link bus as determined in said bus arbitration unit, said plurality of direct memory access channels in each said access unit having a rotating priority therebetween where the channel last serviced has the lowest priority.

Claim 31

A well-logging data acquisition and processing system responsive to signals from well-logging tools contained in a well borehole drilled into the earth's formations, for obtaining well-site measurements from the tools and for generating output logs of well parameters determined from the measurements, the system having a plurality of peripherals units which include a logging tool interface unit comprising: (a) first and second parallel central processors, each including a main memory unit for storing program routines and for storing data comprising messages to and from said plurality of peripheral units, each said processor including (i) a plurality of serial link units, each having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each serial channel sending on transmit lines and receiving on receive lines serial data to and from said plurality of peripheral units, (ii) a processor interface unit responsive to data ready signals, for controlling the transfer of data between the central processor unit and said plurality of serial link units, said interface unit including an internal interface bus, (iii) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit, said plurality of serial link units enabling the simultaneous input/output transfer of data to said plurality of peripheral units, and (iv) a processor bus for data transfer between said central processor unit, its main memory, and said processor interface unit; and (b) a switch means connected to said processor buses and the transmit and receive lines from each channel of each of said serial link units, and responsive to a switch command for controlling which of said first or second processor units is connected to said peripherals for data transfers therebetween.

Claim 32

A well-logging data acquisition and processing system responsive to signals from well-logging tools contained in a well borehole drilled into the earth's formations, for obtaining well-site measurements from the tools and for generating output logs of well parameters determined from the measurements, the system having a plurality of peripherals units which include a logging tool interface unit comprising: (a) first and second parallel central processors, each including a main memory unit for storing program routines and for storing data comprising messages to and from said plurality of peripheral units, each said processor including (i) a plurality of serial link units, each having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each serial channel sending on transmit lines and receiving on receive lines serial data to and from said plurality of peripheral units, (ii) a processor interface unit responsive to data ready signals, for controlling the transfer of data between the central processor unit and said plurality of serial link units, said interface unit including an internal interface bus, (iii) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit, said plurality of serial link units enabling the simultaneous input/output transfer of data to said plurality of peripheral units, and (iv) a processor bus for data transfer between said central processor unit, its main memory, and said processor interface unit; and (b) a switch means connected to said processor buses and the transmit and receive lines from each channel of each of said serial link units, and responsive to a switch command for controlling which of said first or second processor units is connected to said peripherals for data transfers therebetween.

Claim 33

The processing system of claim 28 wherein each said central processing unit includes a system bus interconnecting said microprocessor unit, said processor interface unit and said plurality of serial link units for data transfers therebetween, said buses enabling the transfer of data to occur simultaneously over established data links between (i) said processor unit and said interface unit, (ii) said interface unit and said microprocessor unit, (iii) said interface unit and one of said plurality of serial units, (iv) said microprocessor and one of said plurality of serial units, and (v) each of said plurality of serial link units and any one of said peripherals connected to the plurality of serial input/output channels of said serial link unit.

Claim 34

The processing system of claim 28 wherein said processor interface unit includes: (a) a plurality of interface data registers connected to said processor bus for temporarily storing information being passed between said processor unit and said microprocessor unit or said plurality of serial link units; (b) a direct memory access unit responsive to said microprocessor unit for transferring data between said interface data registers and said serial link units; and (c) means responsive to said microprocessor unit for transferring data between said interface data registers and said main memory, said transferring means and said direct memory access unit responding to initiating signals from said microprocessor unit to enable data comprising outgoing message data to be transferred from main memory to a serial link unit, and vice versa.

Claim 35

The processing system of claim 30 wherein said transferring means obtains data from said main memory independently of processor control.

Claim 36

The processing system of claims 28, 29 or 30 wherein each said serial link unit comprises: (a) a message buffer memory connected to said serial link bus for temporarily storing incoming and outgoing message data for a peripheral connected to said serial link unit; (b) a receive direct memory access unit connected to said serial link bus for controlling the transfer of data between the receive lines of said plurality of serial input/output channels and said buffer memory; (c) a transmit direct memory access unit connected to said serial link bus for controlling the transfer of data between the transmit lines of said plurality of serial input/output channels and said buffer memory; and (d) a plurality of serial controllers each connected to said serial link bus and each associated with one of said plurality of serial input/output channels, each said controller supervising the exchange of data between the peripheral connected to the serial channel and said serial link unit.

Claim 37

The processing system of claim 32 further including a baud rate generator connected to said serial link bus for generating timing signals to determine the transmission rate of the serial data to said peripherals connected to said serial link unit.

Claim 38

The processing system of claim 32 wherein said transmit and said receive direct memory access units each comprise a plurality of direct memory access channels, one for each of said plurality of serial input/output channels of said serial link unit.

Claim 39

The processing system of claim 34 further including a bus arbitration unit for resolving access to said serial link bus between said direct memory access units and any data transfer to said serial link unit from said microprocessor unit or said processor interface unit.

Claim 40

The processing system of claim 35 wherein said direct memory access units alternate in priority as between themselves as to which said access unit will obtain control of said serial link bus as determined by said bus arbitration unit, said plurality of direct memory access channels in each said access unit having a rotating priority threbetween where the channel last serviced has the lowest priority.

Claim 41

A well-logging real time date acquisition and data processing system including a plurality of peripheral unit with which a central processor unit must communicate, the peripheral units including a logging tool interface unit for interfacing to a plurality of tools positioned in a well borehole in the earth, the system comprising: (a) a central processor unit for executing operating routines involving the transfer of data between said processor and said peripherals, said processor (i) coupled to a first plurality of said peripherals for serial data link transfers over transmit and receive lines, and (ii) coupled to a second plurality of said peripherals by a parallel processor bus for the parallel transfer of data to and from said second plurality of peripherals; (b) a plurality of serial data link units coupled to said central processor, each said serial link unit having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each said serial channel sending on transmit lines and receiving on receive lines serial data to and from said first plurality of said peripheral units; and (c) a system bus interconnecting said processor unit to said plurality of serial data link units, said processor bus, said system bus and said plurality of serial link buses enabling the simultaneous transmission of data from said processor to said peripheral units thereby increasing the thru-put rate of said system.

Claim 42

A well-logging real time date acquisition and data processing system including a plurality of peripheral unit with which a central processor unit must communicate, the peripheral units including a logging tool interface unit for interfacing to a plurality of tools positioned in a well borehole in the earth, the system comprising: (a) a central processor unit for executing operating routines involving the transfer of data between said processor and said peripherals, said processor (i) coupled to a first plurality of said peripherals for serial data link transfers over transmit and receive lines, and (ii) coupled to a second plurality of said peripherals by a parallel processor bus for the parallel transfer of data to and from said second plurality of peripherals; (b) a plurality of serial data link units coupled to said central processor, each said serial link unit having a serial link bus and each having a plurality of serial data input/output channels connected to said serial link bus, each said serial channel sending on transmit lines and receiving on receive lines serial data to and from said first plurality of said peripheral units; and (c) a system bus interconnecting said processor unit to said plurality of serial data link units, said processor bus, said system bus and said plurality of serial link buses enabling the simultaneous transmission of data from said processor to said peripheral units thereby increasing the thru-put rate of said system.

Claim 43

The system of claim 37 further including: (a) a processor interface unit responsive to data ready signals, for controlling the transfer of data between said central processor unit and said plurality of serial link units, said interface unit including an internal interface bus, and (b) a microprocessor unit responsive to said processor interface unit and said serial link units for initiating the transfer of data between said plurality of serial link units and said processor interface unit.

Claim 44

The system of claim 38 wherein the simultaneous transfer of data occurs over data links established between (a) said processor unit and said interface unit, (b) said interface unit and said microprocessor unit, (c) said interface unit and one of said plurality of serial units, (d) said microprocessor and one of said plurality of serial units, and (e) each of said plurality of serial link units and any one of said peripherals in said first plurality of peripherals connected to the plurality of serial input/output channels of said serial links unit.

Claim 45

The system of claim 38 wherein said processor interface unit includes: (a) a plurality of interface data registers connected to said processor bus for temporarily storing information being passed between said processor unit and said microprocessor unit or said plurality of serial link units; (b) a direct memory access unit responsive to said microprocessor unit for transferring data between said interface data registers and said serial link units; and (c) means responsive to said microprocessor unit for transferring data between said interface data registers and said main memory, said transferring means and said direct memory access unit responding to initiating signals from said microprocessor unit to enable data comprising outgoing message data to be transferred from main memory to a serial link unit, and vice versa.

Claim 46

The processing system of claim 40 wherein said transferring means obtains data from said main memory independently of processor control.

Claim 47

The processing system of claims 38, 40 or 41 wherein each said serial link unit comprises: (a) a message buffer memory connected to said serial link bus for temporarily storing incoming and outgoing message data for a peripheral connected to said serial link unit; (b) a receive direct memory access unit connected to said serial link bus for controlling the transfer of data between the receive lines of said plurality of serial input/output channels and said buffer memory; (c) a transmit direct memory access unit connected to said serial link bus for controlling the transfer of data between the transmit lines of said plurality of serial input/output channels and said buffer memory; and (d) a plurality of serial controllers each connected to said serial link bus and each associated with one of said plurality of serial input/output channels, each said controller supervising the exchange of data between the peripheral connected to the serial channel and said serial link unit.

Claim 48

The processing system of claim 42 further including a baud rate generator connected to said serial link bus for generating timing signals to determine the transmission rate of the serial data to said peripherals connected to said serial link unit.

Claim 49

The processing system of claim 42 wherein said transmit and said receive direct memory access units each comprise a plurality of direct memory access channels, one for each of said plurality of serial input/output channels of said serial link unit.

Claim 50

The processing system of claim 44 further including a bus arbitration unit for resolving access to said serial link bus between said direct memory access units and any data transfer to said serial link unit from said microprocessor unit or said processor interface unit.

Claim 51

The processing system of claim 45 wherein said direct memory access units alternate in priority as between themselves as to which said access unit will obtain control of said serial link bus as determined by said bus arbitration unit, said plurality of direct memory access channels in each said access unit having a rotating priority therebetween where the channel last serviced has the lowest priority.

Claim 52

The system of claim 38 further including: (a) a second central processor; (b) a second processor interface unit coupled by a second processor bus to said second processor unit; (c) a second microprocessor unit; (d) a second plurality of serial link units; (e) a second system bus coupling said second microprocessor unit and said serial link units to said second processor interface unit; and (f) a switch means connected to said processor buses and the transmit and receive lines from each channel of each said second plurality of serial link units, and responsive to a switch command for controlling which of said processor units is connected to said peripherals for data transfers therewith.

Claim 53

The system of claim 47 wherein all of said peripheral units are connected to said plurality of serial data link units.

Claim 54

A data processing system including peripheral units connected thereto, said system comprising: (a) a central processor unit including a main memory; (b) a plurality of serial input/output channels, each interconnected by a serial link bus and each said serial channel sending on transmit lines and receiving on receive lines serial data to and from a first plurality of the peripheral units; (c) a processor interface unit responsive to signals from said processor unit and said serial link units, for controlling the transfer of data between said central processor unit and said plurality of serial channels, said interface unit including an internal interface bus; and (d) a microprocessor unit responsive to said processor interface unit and said serial input/output channels for initiating the transfer of data between said plurality of serial channels and said processor interface unit, said plurality of serial channels in cooperation with said processor interface unit and said microprocessor unit permitting the simultaneous input/output transfer of data to a plurality of the peripherals in said first plurality of peripherals.

Claim 55

A data processing system including peripheral units connected thereto, said system comprising: (a) a central processor unit including a main memory; (b) a plurality of serial input/output channels, each interconnected by a serial link bus and each said serial channel sending on transmit lines and receiving on receive lines serial data to and from a first plurality of the peripheral units; (c) a processor interface unit responsive to signals from said processor unit and said serial link units, for controlling the transfer of data between said central processor unit and said plurality of serial channels, said interface unit including an internal interface bus; and (d) a microprocessor unit responsive to said processor interface unit and said serial input/output channels for initiating the transfer of data between said plurality of serial channels and said processor interface unit, said plurality of serial channels in cooperation with said processor interface unit and said microprocessor unit permitting the simultaneous input/output transfer of data to a plurality of the peripherals in said first plurality of peripherals.

Claim 56

The processing system of claim 49 further including: (a) a processor bus interconnecting a second plurality of the peripherals units to said central processor unit for data transfers therebetween, said processor bus connecting said processor interface unit to said central processor; and (b) a system bus interconnecting said microprocessor unit, said processor interface unit and a plurality of groups of said channels, each said group comprising a serial link unit where each unit includes its own serial link bus for data transfers therebetween, said buses enabling the transfer of data to occur simultaneously over established data links between (i) said processor unit and a peripheral in said second plurality of peripherals, (ii) said processor unit and said interface unit, (iii) said interface unit and said microprocessor unit, (iv) said interface unit and one of said plurality of serial link units, (v) said microprocessor and one of said plurality of serial link units, and (vi) each of said plurality of serial link units and any one of the peripherals in said first plurality of peripherals connected to the plurality of serial input/output channels of said serial link unit.

Claim 57

The processing system of claim 49 wherein said processor interface unit includes: (a) a plurality of interface data registers connected to said processor bus for temporarily storing information being passed between said processor unit and said microprocessor unit or said plurality of serial channels; (b) a direct memory access unit responsive to said microprocessor unit for transferring data between said interface data registers and said serial channels; and (c) means responsive to said microprocessor unit for transferring data between said interface data registers and said main memory, said transferring means and said direct memory access unit responding to initiating signals from said microprocessor unit to enable data comprising outgoing message data to be transferred from main memory to a serial input/output channel, and vice versa.

Claim 58

The processing system of claim 51 wherein said transferring means obtains data from said main memory independently of processor control.

Claim 59

The processing system of claims 49, 50 or 51 wherein said serial input/output channels comprise: (a) a message buffer memory connected to said serial link bus for temporarily storing incoming and outgoing message data for a peripheral connected to said serial channels; (b) a receive direct memory access unit connected to said serial link bus for controlling the transfer of data between the receive lines of said plurality of serial input/output channels and said buffer memory; (c) a transmit direct memory access unit connected to said serial link bus for controlling the transfer of data between the transmit lines of said plurality of serial input/output channels and said buffer memory; and (d) a plurality of serial controllers each connected to said serial link bus and each associated with one of said plurality of serial input/output channels, each said controller supervising the exchange of data between the peripheral connected to the serial channel and said serial channel.

Claim 60

The processing system of claim 53 further including a baud rate generator connected to said serial link bus for generating timing signals to determine the transmission rate of the serial data to said peripherals connected to said serial channels.

Claim 61

The processing system of claim 53 wherein said transmit and said receive direct memory access units each comprise a plurality of direct memory access channels, one for each of said plurality of serial input/output channels.

Claim 62

The processing system of claim 55 further including a bus arbitration unit for resolving access to said serial link bus between said direct memory access units and any data transfer to said serial channels from said microprocessor unit or said processor interface unit.

Claim 63

The processing system of claim 56 wherein said direct memory access units alternate in priority as between themselves as to which said access unit will obtain control of said serial link bus as determined by said bus arbitration unit, said plurality of direct memory access channels in each said access unit having a rotating priority therebetween where the channel last serviced has the lowest priority.

Claim 64

A well-logging data acquisition and processing system responsive to signals from well-logging tools contained in a well borehole drilled into the earth's formations, for obtaining well-site measurements from the tools and for generating output logs of well parameters determined from the measurements, the system having a plurality of peripherals units which include a logging tool interface unit, the system comprising: (a) first and second parallel central processors, each including a main memory unit for storing program routines and for storing data comprising messages to and from a first plurality of peripheral units, each said processor including (i) a plurality of serial channels, each interconnected by a serial link bus and each serial channel sending on transmit lines and receiving on receive lines serial data to and from said first plurality of the peripheral units, (ii) a processor interface unit responsive to data ready signals, for controlling the transfer of data between the central processor unit and said plurality of serial channels, said interface unit including an internal interface bus, (iii) a microprocessor unit responsive to said processor interface unit and said serial channels for initiating the transfer of data between said plurality of serial channels and said processor interface unit, and (iv) a processor bus for data transfer between said central processor unit, its main memory, said processor interface unit, and a second plurality of said peripheral units; and (b) a switch means connected to said processor buses and the transmit and receive lines from each channel of each of said serial link units and responsive to a switch command for controlling which of said first or second processor units is connected to said peripherals for data transfers therebetween.

Claim 65

A well-logging data acquisition and processing system responsive to signals from well-logging tools contained in a well borehole drilled into the earth's formations, for obtaining well-site measurements from the tools and for generating output logs of well parameters determined from the measurements, the system having a plurality of peripherals units which include a logging tool interface unit, the system comprising: (a) first and second parallel central processors, each including a main memory unit for storing program routines and for storing data comprising messages to and from a first plurality of peripheral units, each said processor including (i) a plurality of serial channels, each interconnected by a serial link bus and each serial channel sending on transmit lines and receiving on receive lines serial data to and from said first plurality of the peripheral units, (ii) a processor interface unit responsive to data ready signals, for controlling the transfer of data between the central processor unit and said plurality of serial channels, said interface unit including an internal interface bus, (iii) a microprocessor unit responsive to said processor interface unit and said serial channels for initiating the transfer of data between said plurality of serial channels and said processor interface unit, and (iv) a processor bus for data transfer between said central processor unit, its main memory, said processor interface unit, and a second plurality of said peripheral units; and (b) a switch means connected to said processor buses and the transmit and receive lines from each channel of each of said serial link units and responsive to a switch command for controlling which of said first or second processor units is connected to said peripherals for data transfers therebetween.

Claim 66

The processing system of claim 58 wherein each said central processing unit includes a system bus interconnecting said microprocessor unit, said processor interface unit and said plurality of serial channels for data transfers therebetween, said plurality of serial channels arranged in groups where each group comprises a serial link unit having its own serial link bus, said buses enabling the transfer of data to occur simultaneously over established data links between (i) said processor unit and said interface unit, (ii) said interface unit and said microprocessor unit, (iii) said interface unit and one of said plurality of serial units, (iv) said microprocessor and one of said plurality of serial units, and (v) each of said plurality of serial link units and any one of said peripherals in said first plurality of peripherals connected to the plurality of serial input/output channels of said serial link unit.

Claim 67

The processing system of claim 58 wherein said processor interface unit includes: (a) a plurality of interface data registers connected to said processor bus for temporarily storing information being passed between said processor unit and said microprocessor unit or said plurality of serial channel; (b) a direct memory access unit responsive to said microprocessor unit for transferring data between said interface data registers and said serial channel; and (c) means responsive to said microprocessor unit for transferring data between said interface data registers and said main memory, said transferring means and said direct memory access unit responding to initiating signals from said microprocessor unit to enable data comprising outgoing message data to be transferred from main memory to a serial input/output channel, and vice versa.

Claim 68

The processing system of claim 60 wherein said transferring means obtains data from said main memory independently of processor control.

Claim 69

The processing system of claims 58, 59 or 60 wherein said serial input/output channels comprise: (a) a message buffer memory connected to said serial link bus for temporarily storing incoming and outgoing message data for a peripheral connected to said serial channels; (b) a receive direct memory access unit connected to said serial link bus for controlling the transfer of data between the receive lines of said plurality of serial input/output channels and said buffer memory; (c) a transmit direct memory access unit connected to said serial link bus for controlling the transfer of data between the transmit lines of said plurality of serial input/output channels and said buffer memory; and (d) a plurality of serial controllers each connected to said serial link bus and each associated with one of said plurality of serial input/output channels, each said controller supervising the exchange of data between the peripheral connected to the serial channel and said serial channel.

Claim 70

The processing system of claim 62 further including a baud rate generator connected to said serial link bus for generating timing signals to determine the transmission rate of the serial data to said peripherals connected to said serial channels.

Claim 71

The processing system of claim 62 wherein said transmit and said receive direct memory access units each comprise a plurality of direct memory access channels, one for each of said plurality of serial input/output channels.

Claim 72

The processing system of claim 64 further including a bus arbitration unit for resolving access to said serial link bus between said direct memory access units and any data transfer to said serial channels from said microprocessor unit or said processor interface unit.

Claim 73

The processing system of claim 65 wherein said direct memory access units alternate in priority as between themselves as to which said access unit will obtain control of said serial link bus as determined in said bus arbitration unit, said plurality of direct memory access channels in each said access unit having a rotating priority therebetween where the channel last serviced has the lowest priority.