High speed data interface buffer for digitally controlled electron beam exposure system

Claim 1

An electron beam exposure system for forming integrated circuit patterns, said system including a source of vector scan pattern data in digital form stored in a mass storage device, a control processor unit, a pattern generator coupled to an electron beam column for generating, within a predetermined time period, discrete circuit patterns from units of data, each unit representative of the location and shape of a predetermined integrated circuit image, and a pattern buffer interface interconnecting said mass storage device and said control processor to said pattern generator, the improvement wherein said pattern buffer interface comprises: a random access buffer memory unit for addressably storing said units of vector scan pattern data, said buffer memory unit being responsive to memory address signals and to read and write signals to execute a memory access cycle within a time period greater than said predetermined time period; write control logic means responsive to an address signal and a plurality of write control signals provided by said control processor for controlling the automatic transfer of a first predetermined number of said units of addressable data from a selected one of said mass storage device and said control processor unit to said first predetermined number of addressable locations in said buffer memory unit by generating, independently of said control processor unit, said first predetermined number of memory address signals and a like number of said write signals; read control logic means responsive to an address signal provided by said control processor unit and being responsive to a plurality of read control signals provided by said control processor unit and said pattern generator for controlling the automatic transfer of a second predetermined number of said addressable units of pattern data from said buffer memory unit to said pattern generator by generating, independently of said control processor unit, said second predetermined number of memory address signals and a like number of read signals in response to read request signals provided by said pattern generator; and buffer interface clock means coupled to said read and said write control logic means for controlling the timing of said automatic transfers of data within said pattern buffer interface, independently of said control processor unit, whereby said pattern generator receives said units of vector scan data at a rate substantially equal to said memory access cycle time period.