Channel interface circuit providing virtual channel number translation and direct memory access

Claim 2

In a data communication system wherein a communication channel (120) carries data messages, each of which contains a header field having a destination address and a virtual channel number, a processor (101) having data, address and control busses and an associated memory (102) connected to said data, address and control busses, a channel interface circuit (100) for interconnecting said data, address and control busses with said communication channel (120) comprising: interface means (119, 201, 204, 205) connected to said communication channel (120) and responsive to a data message appearing thereon for receiving said data message when said destination address identifies said processor (101); wherein said interface means (119, 201, 204, 205) includes incoming state controller means (201) responsive to said received data message for seizing said data, address and control busses; channel control memory means (212, 213) connected to said interface means (119, 201, 204, 205) and responsive to said received data message for translating said virtual channel number to a hardware address identifying a memory storage location in said processor memory (102); driver means (206) connected to both said channel control memory means (212, 213) and to said address bus and responsive to said hardware address for placing said hardware address on said address bus to activate said identified memory store location in said processor memory (102); and wherein said interface means (119, 201, 204, 205) is also connected to said data bus and is responsive to said received data message for directly storing the data portion of said data message as received in said activated memory store location via said data bus.

Claim 3

The invention of claim 1 wherein: said channel control memory means (212, 213) is additionally connected to said data, address and control busses and is responsive to said processor (101) applying said virtual channel number to said address bus for storing memory gueue data identifying available processor memory (102) space output by said processor (101) on said data bus; and wherein said channel interface circuit (100) includes: comparison means (208-210) connected to said channel control memory means (212, 213) and said driver means (206) and responsive to said received data message for applying said hardware address to said driver means (206) when said memory queue data indicates that sufficient space is available in said processor memory (102) to store said received data message.

Claim 4

The invention of claims 1 or 2 wherein said channel interface circuit (100) includes: word count means (207) connected to said driver means (206) and said interface means (119, 201, 204, 205) and responsive to said received data message for incrementing said hardware address stored in said driver means (206) in synchronization with the receipt of said data message.

Claim 5

The invention of claim 3 wherein said word count means (207) is responsive to said received data message for generating an end of word indication when all of said data message has been received by said interface means (119, 201, 204, 205).

Claim 6

The invention of claim 4 wherein said interface means (119, 201, 204, 205) is responsive to said end of word indication for updating the information stored in said channel control memory means (212, 213) via said processor data, address and control busses.

Claim 7

The invention of claim 3 wherein said interface means (119, 201, 204, 205) includes: data buffer means (205) connected to said data bus and said interface means (119, 201, 204, 205) and responsive to said interface means (119, 201, 204, 205) for storing said received data message and for applying said received data message on a byte-by-byte basis to said data bus.

Claim 8

The invention of claim 1 wherein said channel interface circuit (100) includes: outgoing register means (106, 108, 110, 111) connected to said data, address and control busses and responsive to said processor (101) applying said virtual channel number to said address bus for storing outgoing memory queue data identifying the location of an outgoing message in processor memory (102) applied to said data bus by said processor (101); outgoing comparator means (107) connected to said outgoing register means (106, 108, 110, 111) and responsive to said outgoing memory queue data stored therein for generating a message available signal if said outgoing memory queue data indicates that an outgoing data message is stored in said processor memory (102); outgoing control means (103-105) connected to said outgoing register means (106, 108, 110, 111), said outgoing comparator means (107), said address and control busses, and responsive to said message available signal for transferring a hardware address from said outgoing memory queue data identifying a memory storage location in said processor memory (102) to said address bus to read said data message out of said processor memory (102); and wherein said interface means (119) is connected to said outgoing control means (103-105) and is responsive to same for outputting said data message which appears on said data bus on to said communication channel (120).

Claim 9

The invention of claim 7 wherein: said outgoing register means (106, 108, 110, 111) includes read pointer register means (110) for storing said hardware address identifying said memory storage location in said processor memory (102) containing said outgoing data message; and said outgoing control means (103-105) includes DMA address buffer means (104) connected to said read pointer register means (110) and to said address bus wherein said outgoing control means (103-105) is responsive to said message available signal for transferring said hardware address from said read pointer register (110) to said address bus.

Claim 10

The invention of claim 7 wherein said interface means (119, 201, 204, 205) and said outgoing control means (103-105) include processor means (201, 103) responsive to a control algorithm stored therein for regulating the operation of said channel interface circuit (100).

Claim 11

In a data communication system wherein a communication channel (120) carries data messages, each of which contains a header field having a destination address and a virtual channel number, a processor (101) having data, address and control busses and an associated memory connected to said data, address and control busses, a channel interface circuit (100) for interconnecting said data, address and control busses with said communication channel (120) comprising: interface means (119, 201, 204, 205) connected to said communication channel (120) and responsive to a data message appearing thereon for storing said data message when said destination address identifies said processor (101); wherein said interface means (119, 201, 204, 205) includes incoming state controller means (201) responsive to said received data message for seizing said data, address and control busses; channel control memory means (212, 213) connected to said interface means (119, 201, 204, 205) and responsive to said received data message for translating said virtual channel number to a hardware address identifying a memory storage location in said processor memory (102); driver means (206) connected to both said channel control memory means (212, 213) and to said processor address bus and responsive to said hardware address for placing said hardware address on said processor address bus to activate said identified memory store location in said processor memory (102); and wherein said interface means (119, 201, 204, 205) is also connected to said data bus and is responsive to said received data message for transferring the data portion of said data message from said interface means (119, 201, 204, 205) to said activated memory store location in said processor memory (102) via said data bus.

Claim 12

In a data communication system wherein a communication channel (120) carries data messages, each of which contains a header field having a destination address and a virtual channel number, a processor (101) having data, address and control busses and an associated memory connected to said data, address and control busses, a channel interface circuit (100) for interconnecting said data, address and control busses with said communication channel (120) comprising: interface means (119, 201, 204, 205) connected to said communication channel (120) and responsive to a data message appearing thereon for storing said data message when said destination address identifies said processor (101); wherein said interface means (119, 201, 204, 205) includes incoming state controller means (201) responsive to said received data message for seizing said data, address and control busses; channel control memory means (212, 213) connected to said interface means (119, 201, 204, 205) and responsive to said received data message for translating said virtual channel number to a hardware address identifying a memory storage location in said processor memory (102); driver means (206) connected to both said channel control memory means (212, 213) and to said processor address bus and responsive to said hardware address for placing said hardware address on said processor address bus to activate said identified memory store location in said processor memory (102); and wherein said interface means (119, 201, 204, 205) is also connected to said data bus and is responsive to said received data message for transferring the data portion of said data message from said interface means (119, 201, 204, 205) to said activated memory store location in said processor memory (102) via said data bus.

Claim 13

The invention of claim 10 wherein: said channel control memory means (212, 213) is additionally connected to said data, address and control busses and is responsive to said processor (101) applying said virtual channel number to said address bus for storing memory queue data output by said processor or said data bus; and wherein said channel interface circuit (100) includes: comparison means (208-210) connected to said channel control memory means (212, 213) and said driver means (206) and responsive to said received data message for applying said hardware address to said driver means (206) when said memory queue data indicates that sufficient space is available in said processor memory (102) to store said received data message.

Claim 14

The invention of claim 10 or 11 wherein said channel interface circuit (100) includes: word count means (207) connected to said driver means (206) and said interface means (119, 201, 204, 205) and responsive to said received data message for incrementing said hardware address stored in said driver means as said data message is output from said interface means (119, 201, 204, 205) to said data bus.

Claim 15

The invention of claim 12 wherein said word count means (207) is responsive to said received data message for generating an end of word indication when all of said data message has been received by said interface means (119, 201, 204, 205).

Claim 16

The invention of claim 13 wherein said interface means (119, 201, 204, 205) is responsive to said end of word indication for updating the information stored in said channel control memory means (212, 213) via said processor data, address and control busses.

Claim 17

In a data communication system wherein a communication channel (120) carries data messages, each of which contains a header field having a destination address and a virtual channel number, a processor (101) having data, address and control busses and an associated memory (102) connected to said data, address and control busses, a channel interface circuit (100) for interconnecting said data, address and control busses with said communication channel (120) comprising: interface means (119, 201, 204, 205) connected to said communication channel (120) and responsive to a data message appearing thereon for receiving said data message when said destination address identifies said processor (101); wherein said interface means (119, 201, 204, 205) includes incoming state controller means (201) responsive to said received data message for seizing said data, address and control busses; wherein said interface means (119, 201, 204, 205) includes data buffer means (205) responsive to said received data message for storing said data message as received; channel control memory means (212, 213) connected to said interface means (119, 201, 204, 205) and responsive to said received data message for translating said virtual channel number to a hardware address identifying a memory storage location in said processor memory (102); wherein said channel control memory means (212, 213) is additionally connected to said data, address and control busses and is responsive to said processor (101) applying said virtual channel number to said address bus for storing memory queue data output by said processor (101) on said data bus; comparison means (208-210) connected to said channel control memory means (212, 213) and responsive to said received data message for outputting said hardware address if said memory queue data indicates that sufficient space is available in said processor memory (120) to store said data message; driver means (206) connected to both said comparison means (208-210) and to said address bus and responsive to said hardware address for placing said hardware address on said address bus to activate said identified memory store location in said processor memory (120); word count means (207) connected to said driver means (206) and said interface means (119, 201, 204, 205) and responsive to said received data message for incrementing said hardware address stored in said driver means (206) in synchronization with the storage of said data message in said data buffer means (205); and wherein said data buffer means (205) is also connected to said data bus and is responsive to said word count means (207) incrementing said hardware address for directly storing the data portion of said data message as received in said activated memory store location via said data bus.

Claim 18

In a data communication system wherein a communication channel (120) carries data messages, each of which contains a header field having a destination address and a virtual channel number, a processor (101) having data, address and control busses and an associated memory (102) connected to said data, address and control busses, a channel interface circuit (100) for interconnecting said data, address and control busses with said communication channel (120) comprising: interface means (119, 201, 204, 205) connected to said communication channel (120) and responsive to a data message appearing thereon for receiving said data message when said destination address identifies said processor (101); wherein said interface means (119, 201, 204, 205) includes incoming state controller means (201) responsive to said received data message for seizing said data, address and control busses; wherein said interface means (119, 201, 204, 205) includes data buffer means (205) responsive to said received data message for storing said data message as received; channel control memory means (212, 213) connected to said interface means (119, 201, 204, 205) and responsive to said received data message for translating said virtual channel number to a hardware address identifying a memory storage location in said processor memory (102); wherein said channel control memory means (212, 213) is additionally connected to said data, address and control busses and is responsive to said processor (101) applying said virtual channel number to said address bus for storing memory queue data output by said processor (101) on said data bus; comparison means (208-210) connected to said channel control memory means (212, 213) and responsive to said received data message for outputting said hardware address if said memory queue data indicates that sufficient space is available in said processor memory (120) to store said data message; driver means (206) connected to both said comparison means (208-210) and to said address bus and responsive to said hardware address for placing said hardware address on said address bus to activate said identified memory store location in said processor memory (120); word count means (207) connected to said driver means (206) and said interface means (119, 201, 204, 205) and responsive to said received data message for incrementing said hardware address stored in said driver means (206) in synchronization with the storage of said data message in said data buffer means (205); and wherein said data buffer means (205) is also connected to said data bus and is responsive to said word count means (207) incrementing said hardware address for directly storing the data portion of said data message as received in said activated memory store location via said data bus.