Data buffer operating in response to computer halt signal

Claim 2

A buffer for exchanging data between a device and a computer, the former having means for providing a plurality of device signals, the latter having a plurality of lines including a halt line, said halt line being operable to transmit a halt signal when said computer has halted, said buffer comprising: a plurality of transmitting means, including a halt transmitter, each separately connected to predetermined respective ones of said plurality of lines, each of said plurality of transmitting means being operable to transmit its signal to said device, said halt transmitter being connected to said halt line for transmitting said halt signal to said device; and a plurality of receiving means connected between said device and given respective ones of said plurality of lines for coupling to them said device signals from said device, said given respective ones of said lines and said predetermined respective ones of said lines having at least one common member, each one of a predetermined set from said plurality of receiving means having a control means for controlling said predetermined set, said control means having a receive terminal commonly connected to said halt line for enabling operation of said predetermined set in response to said halt signal, the presence and absence of said halt signal on said halt line being effective to enable and disable, respectively, said predetermined set from said plurality of receiving means.

Claim 3

A buffer according to claim 1 wherein a first preselected set from said plurality of transmitting means are connected in antiparallel with a first preselected group from said plurality of receiving means, said first preselected set and group being connected to and controlled by said computer to render them alternately operable to allow simplex communication between said device and said computer.

Claim 4

A buffer according to claim 2 wherein those of said given respective ones of said lines connecting to said first preselected group comprise address lines for said computer.

Claim 5

A buffered test system according to claim 1, 2 or 3 wherein said device is a digital computing device.

Claim 6

A buffer according to claim 2 wherein each of said first preselected set includes a transmit terminal commonly connected to said halt line for transmitting in response to said halt signal but at a time different from when said predetermined set is enabled to operate by said halt signal.

Claim 7

A buffer according to claim 2 wherein a second preselected set from said plurality of transmitting means are connected in antiparallel with a second preselected group from said plurality of controlled receiving means, said second preselected set and group being connected to and controlled by said computer to render them alternately operable to allow simplex communication.

Claim 8

A buffer according to claim 6 wherein those of said given respective ones of said lines connecting to said second preselected group comprise data lines of said computer.

Claim 9

A buffer according to claim 7 wherein said plurality of lines includes a plurality of control lines, and wherein a third preselected set from said plurality of transmitting means are connected to a portion of said control lines, the remaining ones of said control lines being connected to a third preselected group from said plurality of controlled receiving means.

Claim 10

In a tester having at least one unit to be tested and a remote device for providing a plurality of device signals, a buffered test system for testing said unit with said remote device, comprising: a test instrument having a test terminal which is connectable to said unit to measure an operating parameter thereof, said test instrument being operable to provide measurement signals; a computer having a plurality of lines for providing thereon a plurality of signals, at least one of said lines being connected to said test instrument for sending it a signal to commence operation and for receiving from it a measurement signal; a plurality of transmitting means separately connected to predetermined respective ones of said plurality of lines for transmitting to said device their signals, including one corresponding to said measurement signal; and a plurality of receiving means connected between said device and given respective ones of said plurality of lines for coupling to them said device signals from said device, said given respective ones of said lines and said predetermined respective ones of said lines having at least one common member, said plurality of lines including a halt line operable to transmit a halt signal when said computer has halted, said plurality of transmitting means including a halt transmitter connected to said halt line for transmitting said halt signal to said device, each of a predetermined set from said plurality of receiving means having a control means for controlling said predetermined set, said control means having a receive terminal commonly connected to said halt line for enabling operation of said predetermined set, the presence and absence of said halt signal on said halt line being effective to enable and disable, respectively, said predetermined set from said plurality of receiving means.

Claim 11

In a tester having at least one unit to be tested and a remote device for providing a plurality of device signals, a buffered test system for testing said unit with said remote device, comprising: a test instrument having a test terminal which is connectable to said unit to measure an operating parameter thereof, said test instrument being operable to provide measurement signals; a computer having a plurality of lines for providing thereon a plurality of signals, at least one of said lines being connected to said test instrument for sending it a signal to commence operation and for receiving from it a measurement signal; a plurality of transmitting means separately connected to predetermined respective ones of said plurality of lines for transmitting to said device their signals, including one corresponding to said measurement signal; and a plurality of receiving means connected between said device and given respective ones of said plurality of lines for coupling to them said device signals from said device, said given respective ones of said lines and said predetermined respective ones of said lines having at least one common member, said plurality of lines including a halt line operable to transmit a halt signal when said computer has halted, said plurality of transmitting means including a halt transmitter connected to said halt line for transmitting said halt signal to said device, each of a predetermined set from said plurality of receiving means having a control means for controlling said predetermined set, said control means having a receive terminal commonly connected to said halt line for enabling operation of said predetermined set, the presence and absence of said halt signal on said halt line being effective to enable and disable, respectively, said predetermined set from said plurality of receiving means.