US4987530A
Expired / Lapsed
US
⏱️ 0.0 years remaining
Input/output controller for a data processing system
Assignee: EMC Corp
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Filing: 1985-11-15
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Granted: 1991-01-22
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Expires: 2005-11-15
Abstract
Abstract A data processing system having a local memory bus, a main memory coupled to the local memory bus and a host central processing unit coupled to the local memory bus includes a single input/output controller for interfacing a plurality of input/output devices to the local memory bus. The input/output controller includes a plurality of input/output device controllers, each input/output device controller being adapted to be connected to at least one input/output device, a single microprocessor for managing the overall operations of the input/output controller, a single buffer memory for storing a program of instructions for the microprocessor and temporarily storing data received from the input/output devices and a gate array for interfacing all of the input/output device controllers to the local memory bus.
Inventors
- 👤 Eric M. Wagner
- 👤 Martin Kiernicki
- 👤 John L. Freeman
Bibliographic Details
Application Number
—
Jurisdiction
US
Data Source
google_patents
Last Synchronized
2026-10-26 06:58
CPC Classifications
G; G06; G06F; G06F3/00; G06F3/06; G06F3/0601; G06F13/00; G06F13/10; G06F13/12; G06F13/124; G06F13/14; G06F13/16; G06F13/18; G06F3/0668; G06F3/0671; G06F3/0673
Claims Analysis
Total Claims: 3
Claim 1
Independent Claim
189 words
A data processing system comprising: a. a local memory bus, b. a central processing unit connected to said local memory bus, c. a main memory section connected to said local memory bus, and d. a subsystem for connecting said data processing system to a plurality of input/output devices, said subsystem comprising: i. a plurality of input/output device controllers, ii. a single microprocessor for controlling the operations of said subsystem, iii. a buffer RAM for storing a program for operating said single microprocessor, iv. a gate array for interfacing said input/output device controllers to said main memory section and managing the flow of data between said input/output device controllers, said microprocessor, said main memory section and said buffer RAM, subsystem further includes: v. a host microcode data transceiver for transmitting data between the subsystem and the CPU, vi. a buffer RAM data transceiver for transmitting data between the buffer RAM and the microprocessor section, vii. a power up PROM for holding an initialization program for the subsystem, viii. an address latch for holdling the valid address for accessing the host microcode data transceiver, and ix. a pair of buffer RAMS.
Claim 2
Dependent Claim
189 words
A data processing system comprising: a. a local memory bus, b. a central processing unit connected to said local memory bus, c. a main memory section connected to said local memory bus, and d. a subsystem for connecting said data processing system to a plurality of input/output devices, said subsystem comprising: i. a plurality of input/output device controllers, ii. a single microprocessor for controlling the operations of said subsystem, iii. a buffer RAM for storing a program for operating said single microprocessor, iv. a gate array for interfacing said input/output device controllers to said main memory section and managing the flow of data between said input/output device controllers, said microprocessor, said main memory section and said buffer RAM, subsystem further includes: v. a host microcode data transceiver for transmitting data between the subsystem and the CPU, vi. a buffer RAM data transceiver for transmitting data between the buffer RAM and the microprocessor section, vii. a power up PROM for holding an initialization program for the subsystem, viii. an address latch for holdling the valid address for accessing the host microcode data transceiver, and ix. a pair of buffer RAMS.
Claim 3
Dependent Claim
91 words
The data processing system of claim 1 and wherein said subsystem further includes: a. a plurality of DMA transceivers, each transceiver transferring data between the buffer RAM and a particular input/output device, b. a buffer RAM address register for holding a valid buffer RAM address, c. a buffer RAM local bus data transceiver for transferring data between the local bus and the buffer RAM, and, d. a local bus address/command latching transceiver for holding addresses and local bus command bits for data transfer between the local bus and the buffer RAM.
References Cited (Backward Citations)
USPTO Annuity & Maintenance Windows
| Annuity Stage | Window Opens | Payment Deadline | Surcharge Period Until | Estimated Fee | Status |
|---|---|---|---|---|---|
| 3.5 Years (Year 4) | 1994-01-21 | 1994-07-23 | 1995-01-22 | $2000.00 | Window Closed / Lapsed |
| 7.5 Years (Year 8) | 1998-01-21 | 1998-07-23 | 1999-01-22 | $3760.00 | Window Closed / Lapsed |
| 11.5 Years (Year 12) | 2002-01-21 | 2002-07-23 | 2003-01-22 | $7700.00 | Window Closed / Lapsed |