Merged complementary bipolar and MOS means and method

Claim 2

A merged semiconductor device structure comprising: a substrate having first and second laterally isolated semiconductor regions; a first MOS transistor having a source and a drain of a first conductivity type, and a channel located between the source and drain of the first conductivity type, wherein the first MOS transistor is located in the first region; a first bipolar transistor having a base of the first conductivity type and emitter and collector of a second conductivity type opposite the first conductivity type, located in the first region; a second MOS transistor having a source and a drain of the second conductivity type, and a channel located between the source and drain of the second conductivity type, wherein the second MOS transistor is located in the second region; and a second bipolar transistor having a base of the second conductivity type and emitter and collector of a first conductivity type located in the second region.

Claim 3

The device of claim 1 wherein the source of the first MOS transistor is connected to the collector of the first bipolar transistor, the source of the second MOS transistor is connected to the collector of the second bipolar transistor, the emitter of the first bipolar transistor is connected to the emitter of the second bipolar transistor, the base of the first bipolar transistor is connected to the base of the second bipolar transistor, and a gate of the first MOS transistor is connected to a gate of the second MOS transistor.

Claim 4

The device of claim 1 wherein the source and drain of the first MOS transistor and the emitter and a collector contact of the second bipolar transistor are doped regions having a first depth from a principal device surface, and wherein the source and drain of the second MOS transistor and the emitter and a collector contact of the first bipolar transistor are doped regions having a second depth from the device surface different than the first depth.

Claim 5

The device of claim 3 wherein the first depth exceeds the second depth.

Claim 6

A merged semiconductor device structure comprising: a substrate having first and second semiconductor regions separated by a lateral isolation means, each region having opposed first and second ends, wherein the first and second regions are arranged side-by-side so that the first and second ends of the first region are, except for part of the isolation means, adjacent the first and second ends, respectively, of the second region; a first MOS transistor located in the first region and having a first source and drain of a first conductivity type, a first channel and first source, drain and gate contacts; a first bipolar transistor located in the first region and having a first emitter of a second conductivity type opposite the first type, a first base of the first conductivity type in common with the first drain, a first collector of the first conductivity type underlying the base, and first emitter, base, and collector contacts, wherein the first collector contact is shorted to the first source contact and the first drain contact and first base contact are common; a second MOS transistor located in the second region and having a second source and drain of a second conductivity type, a second channel and second source, drain and gate contacts; a second bipolar transistor located in the second region and having a second emitter of the first conductivity type, a second base of the second conductivity type in common with the second drain, a second collector of the second conductivity type underlying the second base, and second emitter, base, and collector contacts, wherein the second collector contact is shorted to the second source contact and the second drain contact and second base contact are common; wherein the first and second emitter contacts are arranged near the first ends of the first and second regions, the first and second base contacts are arranged next in line toward the second ends and spaced apart from the first and second emitter contacts, respectively, the first and second gate contacts are arranged still next in line toward the second ends and spaced apart from the first and second base contacts, respectively, and the first and second collector contacts are arranged near the first ends; and wherein the first and second emitter contacts are interconnected, the first and second base contacts are interconnected, and first and second gate contacts of the first and second transistors are interconnected, by substantially parallel conductors passing over the part of the isolation means.

Claim 7

A merged semiconductor device structure comprising: a substrate having first and second semiconductor regions separated by a lateral isolation means, each region having opposed first and second ends, wherein the first and second regions are arranged side-by-side so that the first and second ends of the first region are, except for part of the isolation means, adjacent the first and second ends, respectively, of the second region; a first MOS transistor located in the first region and having a first source and drain of a first conductivity type, a first channel and first source, drain and gate contacts; a first bipolar transistor located in the first region and having a first emitter of a second conductivity type opposite the first type, a first base of the first conductivity type in common with the first drain, a first collector of the first conductivity type underlying the base, and first emitter, base, and collector contacts, wherein the first collector contact is shorted to the first source contact and the first drain contact and first base contact are common; a second MOS transistor located in the second region and having a second source and drain of a second conductivity type, a second channel and second source, drain and gate contacts; a second bipolar transistor located in the second region and having a second emitter of the first conductivity type, a second base of the second conductivity type in common with the second drain, a second collector of the second conductivity type underlying the second base, and second emitter, base, and collector contacts, wherein the second collector contact is shorted to the second source contact and the second drain contact and second base contact are common; wherein the first and second emitter contacts are arranged near the first ends of the first and second regions, the first and second base contacts are arranged next in line toward the second ends and spaced apart from the first and second emitter contacts, respectively, the first and second gate contacts are arranged still next in line toward the second ends and spaced apart from the first and second base contacts, respectively, and the first and second collector contacts are arranged near the first ends; and wherein the first and second emitter contacts are interconnected, the first and second base contacts are interconnected, and first and second gate contacts of the first and second transistors are interconnected, by substantially parallel conductors passing over the part of the isolation means.

Claim 8

A monolithic complementary bipolar and complementary MOS device comprising: first and second active areas isolated from each other by an isolation region, wherein the first active area comprises a semiconductor tub of a first conductivity type in which is formed a drain/base region of a second conductivity type; a first source region of the second conductivity type, wherein the source and drain/base regions are separated by a first channel region; and an emitter of the first conductivity type, formed in the drain/base region; wherein the second active area comprises a semiconductor tub of the second conductivity type in which is formed a base region of the first conductivity type; a drain region of the first conductivity type which is coupled to the base region; a second source region of the first conductivity type which is separated from the drain region by a second channel region; and an emitter of the second conductivity type formed in the base region and isolated from the semiconductor tub of the second conductivity type; a first gate opverlying the first channel region; and a second gate overlying the second channel region.

Claim 9

A monolithic complementary bipolar and complementary MOS device comprising: first and second active areas isolated from each other by an isolation region, wherein the first active area comprises a semiconductor tub of a first conductivity type in which is formed a drain/base region of a second conductivity type; a first source region of the second conductivity type, wherein the source and drain/base regions are separated by a first channel region; and an emitter of the first conductivity type, formed in the drain/base region; wherein the second active area comprises a semiconductor tub of the second conductivity type in which is formed a base region of the first conductivity type; a drain region of the first conductivity type which is coupled to the base region; a second source region of the first conductivity type which is separated from the drain region by a second channel region; and an emitter of the second conductivity type formed in the base region and isolated from the semiconductor tub of the second conductivity type; a first gate opverlying the first channel region; and a second gate overlying the second channel region.

Claim 10

The device of claim 6 wherein the emitter of the first conductivity type is coupled to the drain/base region, the drain/base region is coupled to the drain region of the first conductivity type, and the first gate is coupled to the second gate.

Claim 11

The device of claim 7 wherein the semiconductor tub of the first conductivity type is electrically connected to the first source and the semiconductor tub of the second conductivity type is electrically connected to the second source.

Claim 12

The device of claim 7 wherein the emitter of the first conductivity type and the emitter of the second conductivity type are each adjacent to the isolation region and separated from each other by the isolation region.

Claim 13

The device of claim 7 wherein the semiconductor tubs of the first and second type are substantially the same thickness.

Claim 14

The device of claim 7 wherein the first source, the drain/base region and the emitter of the second conductivity type have substantially the same thickness.

Claim 15

The device of claim 7 wherein the emitter of the first conductivity type, the second source, and the drain region are substantially the same thickness.

Claim 16

The device of claim 7 wherein the first channel region is substantially intrinsic.

Claim 17

The device of claim 7 wherein the first channel region of the first conductivity type.