Fabrication methods for high performance lateral bipolar transistors

Claim 2

A lateral PNP transistor comprising: a monocrystalline semiconductor body having an N type principal surface; a buried N+ region within said body; a P type emitter region in said principal surface of said body; an N type base region in said body around the side periphery of said emitter region; a P type collector region in said body surrounding said base region; a first P+ polycrystalline silicon layer in physical and electrical ohmic contact with said collector region acting as collector contact for said collector region; a first insulator layer on the top surface of said first P+ polycrystalline layer; a second P+ polycrystalline silicon layer on the surface of said body in physical and electrical ohmic contact with said emitter region; a second insulator layer on the top surface of said second polycrystalline layer; a vertical insulator layer on the edge of said first polycrystalline silicon layer; said first insulator layer and said vertical insulator layer electrically separates said first and second polycrystalline layers; said N base region at its surface is located underneath the width of said vertical insulator layer; an N+ reach-through region extending from the surface of said body to said buried N+ region and dielectrically isolated at the surface from the said emitter and base regions at the surface; and an electrical contact to said N+ reach-through region through said N+ buried layer to said base region.

Claim 3

The lateral PNP transistor of claim 1 wherein said vertical insulator has a width which is equal to the desired base width of said lateral PNP plus the lateral diffusions of the collector and emitter junctions of said lateral PNP.

Claim 4

The lateral PNP transistor of claim 2 wherein said width of said vertical insulator is between about 100 to 500 nanometers.

Claim 5

The lateral PNP transistor of claim 1 and further comprising a vertical NPN transistor, a dielectric isolation surrounding both said vertical NPN and lateral PNP and the isolation extending to a depth which isolates said buried N+ region from other such regions, and wherein the said buried N+ region is connected as the collector of said vertical NPN.

Claim 6

A lateral PNP transistor comprising: a monocrystalline semiconductor body having an N type principal surface and a groove therein with substantially vertical sides; a buried N+ region within said body and below said groove; a silicon dioxide layer at the bottom of said groove; a P type emitter region in said body around the side periphery of said groove; an N type base region in said body surrounding said emitter region on the other side of the emitter region from said groove; a P type collector region in said body surrounding said base region; a first P+ polycrystalline silicon layer on the surface of said body in physical and electrical contact with said collector region; a first insulator layer on the top surface of said first polycrystalline layer; a second P+ polycrystalline silicon layer filling said groove and acting as emitter contact for said emitter region; a second insulator layer on the top surface of said second polycrystalline layer; a vertical insulator layer on the edge of said first polycrystalline silicon layer; said first insulator layer and said vertical layer electrically separates said first and second polycrystalline layers; portions of said vertical insulator layer being in alignment with the vertical sides of said groove; said N base region at its surface is located underneath, the width of said vertical insulator layer; an N+ reach-through region extending from the surface of said body to said buried N+ region and dielectrically isolated at the surface from the said emitter and base regions at the surface; and an electrical contact to said N+ reach-through region through said N+ buried layer to said base region.

Claim 7

A lateral PNP transistor comprising: a monocrystalline semiconductor body having an N type principal surface and a groove therein with substantially vertical sides; a buried N+ region within said body and below said groove; a silicon dioxide layer at the bottom of said groove; a P type emitter region in said body around the side periphery of said groove; an N type base region in said body surrounding said emitter region on the other side of the emitter region from said groove; a P type collector region in said body surrounding said base region; a first P+ polycrystalline silicon layer on the surface of said body in physical and electrical contact with said collector region; a first insulator layer on the top surface of said first polycrystalline layer; a second P+ polycrystalline silicon layer filling said groove and acting as emitter contact for said emitter region; a second insulator layer on the top surface of said second polycrystalline layer; a vertical insulator layer on the edge of said first polycrystalline silicon layer; said first insulator layer and said vertical layer electrically separates said first and second polycrystalline layers; portions of said vertical insulator layer being in alignment with the vertical sides of said groove; said N base region at its surface is located underneath, the width of said vertical insulator layer; an N+ reach-through region extending from the surface of said body to said buried N+ region and dielectrically isolated at the surface from the said emitter and base regions at the surface; and an electrical contact to said N+ reach-through region through said N+ buried layer to said base region.

Claim 8

The lateral PNP transistor of claim 5 wherein said vertical insulator has a width which is equal to the desired base width of said lateral PNP plus the lateral diffusions of the collector and emitter junctions of said lateral PNP.

Claim 9

The lateral PNP transistor of claim 6 wherein said width of said vertical insulator is between about 100 to 500 nanometers.

Claim 10

The lateral PNP transistor of claim 5 and further comprising a vertical NPN transistor, a dielectric isolation surrounding both said vertical NPN and lateral PNP and the isolation extending to a depth which isolates said buried N+ region from other such regions, and wherein the said buried N+ region is also connected as the collector of said vertical NPN.

Claim 11

A lateral PNP and vertical NPN transistor structure comprising: a monocrystalline semiconductor body composed of a P type substrate, and N type epitaxial layer thereover, a buried pattern of N+ type regions located at the interface of said substrate and said epitaxial layer; a deep dielectric isolation region surrounding the designated said PNP and NPN transistor regions and extending into the said body so as to fully isolated one of said pattern of buried N+ region from the others; a P type emitter region is said body; an N type base region in said body surrounding the side periphery said emitter region; a P type collector region in said body surrounding said base region; a first P+ polycrystalline silicon layer in physical and ohmic electrical contact to said collector region acting as collector contact for said collector region; a first insulator layer on top of said first P+ polycrystalline layer; a second P+ polycrystalline silicon layer on the surface of said body in physical and electrical contact with said emitter region; a second insulator layer on the top surface of said second P+ polycrystalline layer; a vertical insulator layer on the edge of said second polycrystalline silicon layer; said first insulator layer and said vertical layer electrically separates said first and second polycrystalline layers. said N base region at its surface is located underneath the width of said vertical insulator layer; adjacent to said PNP transistor is a vertical NPN transistor which includes an N+ type emitter region, a P type base region surrounding said emitter, a third P+ polycrystalline layer in electrical contact with said base region, a N+ type polycrystalline silicon layer in electrical contact with said emitter region; an N+ reach-through region extending from the surface of said body. To said buried N+ region wherein the N+ reach-through region is the base contact through the N+ buried region of said lateral PNP and the collector contact through the N+ buried region of the vertical NPN; and surface dielectric isolation regions for isolating the NPN base-emitter region, the N+ reach-through region and the PNP region from one another.

Claim 12

A lateral PNP and vertical NPN transistor structure comprising: a monocrystalline semiconductor body composed of a P type substrate, and N type epitaxial layer thereover, a buried pattern of N+ type regions located at the interface of said substrate and said epitaxial layer; a deep dielectric isolation region surrounding the designated said PNP and NPN transistor regions and extending into the said body so as to fully isolated one of said pattern of buried N+ region from the others; a P type emitter region is said body; an N type base region in said body surrounding the side periphery said emitter region; a P type collector region in said body surrounding said base region; a first P+ polycrystalline silicon layer in physical and ohmic electrical contact to said collector region acting as collector contact for said collector region; a first insulator layer on top of said first P+ polycrystalline layer; a second P+ polycrystalline silicon layer on the surface of said body in physical and electrical contact with said emitter region; a second insulator layer on the top surface of said second P+ polycrystalline layer; a vertical insulator layer on the edge of said second polycrystalline silicon layer; said first insulator layer and said vertical layer electrically separates said first and second polycrystalline layers. said N base region at its surface is located underneath the width of said vertical insulator layer; adjacent to said PNP transistor is a vertical NPN transistor which includes an N+ type emitter region, a P type base region surrounding said emitter, a third P+ polycrystalline layer in electrical contact with said base region, a N+ type polycrystalline silicon layer in electrical contact with said emitter region; an N+ reach-through region extending from the surface of said body. To said buried N+ region wherein the N+ reach-through region is the base contact through the N+ buried region of said lateral PNP and the collector contact through the N+ buried region of the vertical NPN; and surface dielectric isolation regions for isolating the NPN base-emitter region, the N+ reach-through region and the PNP region from one another.

Claim 13

The lateral PNP transistor of claim 9 wherein said vertical insulator has a width which is equal to the desired base width of said lateral PNP plus the lateral diffusions of the collector and emitter junctions of said lateral PNP.

Claim 14

The lateral PNP transistor of claim 10 wherein said width of said vertical insulator is between about 100 to 500 nanometers.

Claim 15

A lateral PNP and vertical NPN transistor structure comprising: a monocrystalline semiconductor body composed of a P type substrate an N type epitaxial layer thereover, a buried pattern of N+ type regions located at the interface of said substrate and said epitaxial layer; a deep dielectric isolation region surrounding the designated said PNP and NPN transistor regions and extending into the said body so as to fully isolated one of said pattern of buried N+ regions from the others; a groove having substantially vertical sides extending from the surface of said epitaxial layer into said PNP region; a silicon dioxide layer at the bottom of said groove; a P type emitter region in said body around the side periphery said groove; an N type base region in said body surrounding said emitter region on the other side of the emitter region from said groove; a P type collector region in said body surrounding said base region; a first P+ polycrystalline silicon layer on the surface of said body in physical and electrical contact with said collector region; a first insulator layer on the top surface of said first polycrystalline layer; a second P+ polycrystalline silicon layer filling said groove and acting as emitter contact for said emitter region; a second insulator layer on the top surface of said second polycrystalline layer; a vertical insulator layer on the edge of said first polycrystalline silicon layer; said first insulator layer and said vertical layer electrically separate said first and second polycrystalline layers; portions of said vertical insulator layer being in alignment with the vertical sides of said groove; said N base region at its surface is located underneath the width of said vertical insulator layer; adjacent to said PNP transistor is a vertical NPN transistor which includes an N+ type emitter region, a P type base region surrounding said emitter, a third P+ polycrystalline layer in electrical contact with said base region, a N+ type polycrystalline silicon layer in electrical contact with said emitter region; an N+ reach-through region extending from the surface of said body to said buried N+ region wherein the N+ reach-through region is the base contact through the N+ buried region of said lateral PNP and the collector contact through the N+ buried region of the vertical NPN; and surface dielectric isolation regions for isolating the NPN base-emitter region the N+ region-through region and the PNP region from one another.

Claim 16

A lateral PNP and vertical NPN transistor structure comprising: a monocrystalline semiconductor body composed of a P type substrate an N type epitaxial layer thereover, a buried pattern of N+ type regions located at the interface of said substrate and said epitaxial layer; a deep dielectric isolation region surrounding the designated said PNP and NPN transistor regions and extending into the said body so as to fully isolated one of said pattern of buried N+ regions from the others; a groove having substantially vertical sides extending from the surface of said epitaxial layer into said PNP region; a silicon dioxide layer at the bottom of said groove; a P type emitter region in said body around the side periphery said groove; an N type base region in said body surrounding said emitter region on the other side of the emitter region from said groove; a P type collector region in said body surrounding said base region; a first P+ polycrystalline silicon layer on the surface of said body in physical and electrical contact with said collector region; a first insulator layer on the top surface of said first polycrystalline layer; a second P+ polycrystalline silicon layer filling said groove and acting as emitter contact for said emitter region; a second insulator layer on the top surface of said second polycrystalline layer; a vertical insulator layer on the edge of said first polycrystalline silicon layer; said first insulator layer and said vertical layer electrically separate said first and second polycrystalline layers; portions of said vertical insulator layer being in alignment with the vertical sides of said groove; said N base region at its surface is located underneath the width of said vertical insulator layer; adjacent to said PNP transistor is a vertical NPN transistor which includes an N+ type emitter region, a P type base region surrounding said emitter, a third P+ polycrystalline layer in electrical contact with said base region, a N+ type polycrystalline silicon layer in electrical contact with said emitter region; an N+ reach-through region extending from the surface of said body to said buried N+ region wherein the N+ reach-through region is the base contact through the N+ buried region of said lateral PNP and the collector contact through the N+ buried region of the vertical NPN; and surface dielectric isolation regions for isolating the NPN base-emitter region the N+ region-through region and the PNP region from one another.

Claim 17

The lateral PNP transistor of claim 12 wherein said vertical insulator has a width which is equal to the desired base width of said lateral PNP plus the lateral diffusions of the collector and emitter junctions of said lateral PNP.

Claim 18

The lateral PNP transistor of claim 13 wherein said width of said vertical insulator is between about 100 to 500 nanometers.