← Back to Patent Explorer
US5111276A Expired / Lapsed US ⏱️ 0.0 years remaining

Thick bus metallization interconnect structure to reduce bus area

Assignee: National Semiconductor Corp
•
Filing: 1990-11-19
•
Granted: 1992-05-05
•
Expires: 2010-11-19
📄 Original PDF 🌐 Google Patents 🔄 Sync Now

Abstract

Abstract There is disclosed a structure for self aligned and non-self aligned power and ground buses and interconnects for integrated circuits which are thicker than normal conductors. This enables them to withstand higher current densities without adverse electromigration effects. There is also disclosed a method for making such structures.

Inventors

  • 👤 Hemraj Hingarh
  • 👤 Andres D. Asuncion
  • 👤 Michael Thomas
  • 👤 Robert Brown

Bibliographic Details

Application Number —
Jurisdiction US
Data Source google_patents
Last Synchronized 2026-11-08 11:48
CPC Classifications
H; H10; H10W; H10W20/00; H10W20/01; H10W20/031; H10W20/40; H10W20/41; H10W20/427

Claims Analysis

Total Claims: 17
Claim 1
Independent Claim 189 words
A metallization structure for a horizontally extending power bus region and horizontally extending interconnect lines in an integrated circuit comprising: a semiconductor substrate having circuit elements formed therein; a conductive bus region; horizontally extending conductive interconnect lines coupled to said circuit elements and to said power bus region for transmitting power from said power bus region to said circuit elements; said horizontally extending power bus region and said horizontally extending interconnect lines being formed of a first horizontally extending conductive layer of a first predetermined thickness and insulated from said substrate except for the connections with said elements; said power bus region further being formed of a second horizontally extending conductive layer disposed upon and in physical contact with an upper surface of and in electrical contact with selected portions of said first horizontally extending conductive layer, said second horizontally extending conductive layer having a second predetermined thickness; and, said metallization structure thereby defining a power bus region with a thickness greater than the thickness of said interconnect lines wherein said first horizontally extending conductive layer is integral both to said interconnect lines and to said power bus region.
Claim 2
Dependent Claim 189 words
A metallization structure for a horizontally extending power bus region and horizontally extending interconnect lines in an integrated circuit comprising: a semiconductor substrate having circuit elements formed therein; a conductive bus region; horizontally extending conductive interconnect lines coupled to said circuit elements and to said power bus region for transmitting power from said power bus region to said circuit elements; said horizontally extending power bus region and said horizontally extending interconnect lines being formed of a first horizontally extending conductive layer of a first predetermined thickness and insulated from said substrate except for the connections with said elements; said power bus region further being formed of a second horizontally extending conductive layer disposed upon and in physical contact with an upper surface of and in electrical contact with selected portions of said first horizontally extending conductive layer, said second horizontally extending conductive layer having a second predetermined thickness; and, said metallization structure thereby defining a power bus region with a thickness greater than the thickness of said interconnect lines wherein said first horizontally extending conductive layer is integral both to said interconnect lines and to said power bus region.
Claim 3
Dependent Claim 27 words
A structure as defined in claim 1 further comprising a third conductive layer interposed between said conductive power bus and said circuit elements formed on said substrate.
Claim 4
Dependent Claim 24 words
A structure as defined in claim 1 further comprising a third conductive layer formed above said power bus and in electrical contact with it.
Claim 5
Dependent Claim 42 words
A structure as defined in claim 1 wherein said first and second conductive layers of said power bus are self aligned such that there is never any mask registration error overlap between said first and second conductive layers of said power bus.
Claim 6
Dependent Claim 83 words
The structure of claim 4 wherein said first conductive layer is chosen from a first class of conductive materials which are subject to etching by a first etching process that will not etch the material of said second layer and said second conductive layer is chosen from a second class of conductive materials not subject to etching by the first etching process and which are subject to etching by a second etching process that will not etch the material of said first layer.
Claim 7
Dependent Claim 48 words
The structure of claim 5 wherein said first conductive layer is chosen from the group comprising aluminum, tungsten or silicide and said second layer is one of the other materials in this group which is not subject to etching by the process chosen to etch said first layer.
Claim 8
Dependent Claim 19 words
The structure of claim 5 wherein said first conductive layer is aluminum and the second conductive layer is tungsten.
Claim 9
Dependent Claim 19 words
The structure of claim 5 wherein said first conductive layer is aluminum and the second conductive layer is silicide.
Claim 10
Dependent Claim 81 words
The structure of claim 1 wherein said first conductive layer is chosen from a first class of conductive materials which are subject to etching by a first etching process that will not etch the material of said second layer and said second conductive layer is chosen from a second class of conductive materials not subject to etching by the first etching process and which are subject to etching by a second etching process that will not etch said first conductive layer.
Claim 11
Dependent Claim 38 words
The structure of claim 1 wherein said second layer forming said bus is deposited to have an upper surface higher above said substrate than the portions of the upper surface of said first layer forming said interconnect lines.
Claim 12
Dependent Claim 28 words
The structure of claim 10 wherein the portions of said first layer forming said interconnect lines and said bus are disposed substantially the same height above said substrate.
Claim 13
Dependent Claim 25 words
The structure of claim 1 further comprising a third conductive layer interposed between said conductive power bus and said circuit elements formed on said substrate.
Claim 14
Dependent Claim 24 words
The structure as defined in claim 1 further comprising a third conductive layer formed above said power bus and in electrical contact with it.
Claim 15
Dependent Claim 43 words
The structure of claim 1 wherein said first and second conductive layers of said power bus are self aligned such that there is never any mask registration error overlap at the edges of said first and second conductive layers of said power bus.
Claim 16
Dependent Claim 86 words
The structure of claim 4 wherein said first conductive layer is chosen from a first class of conductive materials which are subject to etching by a first plasma etching process that will not etch the material of said second layer and said second conductive material is chosen from a second class of conductive materials not subject to etching by the first plasma etching process and which are subject to etching by a second plasma etching process that will not etch the material of the first layer.
Claim 17
Dependent Claim 84 words
The structure of claim 1 wherein said first conductive layer is chosen from a first class of conductive materials which are subject to etching by a first plasma etching process that will not etch the material of said second layer and said second conductive layer is chosen from a second class of conductive materials not subject to etching by the first plasma etching process and which are subject to etching by a second plasma etching process that will not etch the first conductive layer.

USPTO Annuity & Maintenance Windows

Annuity Stage Window Opens Payment Deadline Surcharge Period Until Estimated Fee Status
3.5 Years (Year 4) 1995-05-05 1995-11-04 1996-05-05 $2000.00 Window Closed / Lapsed
7.5 Years (Year 8) 1999-05-05 1999-11-04 2000-05-05 $3760.00 Window Closed / Lapsed
11.5 Years (Year 12) 2003-05-05 2003-11-04 2004-05-05 $7700.00 Window Closed / Lapsed

Assigned Categories & Tags

No categories assigned to this patent yet.

Assign Category Tag