Multicell semiconductor memory device

Claim 2

A semiconductor device comprising a semiconductor substrate; a plurality of memory cells constituting a memory cell array on a surface of the semiconductor substrate; a plurality of first conductive layers on the semiconductor substrate, each first conductive layer in contact with two memory cells; and a plurality of second conductive layers, each second conductive layer in contact with multiple first conductive layers.

Claim 3

The semiconductor device according to claim 1, wherein said plurality of second conductive layers are located at intermediate locations between adjacent memory cells.

Claim 4

The semiconductor device according to claim 1, wherein a first insulating film is on said array of memory cells, and each first conductive layer is connected to corresponding diffusion regions via a first contact hole in said first insulating film.

Claim 5

The semiconductor device according to claim 3, wherein a second insulating film is over said first insulating film and said plurality of first conductive layers and second plurality of conductive layers are such that they are in contact with said plurality of first conductive layers via a second contact hole in the second insulating film.

Claim 6

A semiconductor device comprising a semiconductor substrate; a plurality of memory cells constituting a memory cell array on a surface of the semiconductor substrate; a plurality of first conductive layers over the semiconductor substrate each in contact with two adjacent memory cells in the memory cell array, projections of the two adjacent memory cells extending in a mutually opposite rotation, and a second conductive layer over the first conductive layers in contact with multiple ones of the first conductive layers.

Claim 7

A semiconductor device comprising a semiconductor substrate; a plurality of memory cells constituting a memory cell array on a surface of the semiconductor substrate; a plurality of first conductive layers over the semiconductor substrate each in contact with two adjacent memory cells in the memory cell array, projections of the two adjacent memory cells extending in a mutually opposite rotation, and a second conductive layer over the first conductive layers in contact with multiple ones of the first conductive layers.

Claim 8

A semiconductor device comprising a semiconductor substrate; a plurality of memory cells constituting a memory cell array on a surface of the semiconductor substrate; a plurality of first conductive layers over the semiconductor substrate each in contact with two adjacent memory cells in the memory well array, projections of the two adjacent memory cells extending in a mutually opposite rotation, and a second conductive layer over the first conductive layers in contact with multiple ones of the first conductive layers, wherein said second conductive layer is located at an intermediate location of said two adjacent memory arrays.

Claim 9

A semiconductor device comprising a semiconductor substrate; a plurality of memory cells constituting a memory cell array on a surface of the semiconductor substrate; a plurality of first conductive layers over the semiconductor substrate each in contact with two adjacent memory cells in the memory well array, projections of the two adjacent memory cells extending in a mutually opposite rotation, and a second conductive layer over the first conductive layers in contact with multiple ones of the first conductive layers, wherein said second conductive layer is located at an intermediate location of said two adjacent memory arrays.

Claim 10

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; an array of memory cells, each cell having a diffusion region of a second conductivity type in a surface portion of said substrate; a plurality of first conductive layers of the second conductivity type provided for the memory cells respectively each having a portion in contact with said diffusion region of the corresponding memory cell; and a plurality of second conductive layers provided for the first conductive layers, each having multiple contacting portions, each contacting portion contacting a respective first conductive layer, each contacting portion being laterally removed from the memory cell contacting the corresponding first conductive layer.

Claim 11

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; an array of memory cells, each cell having a diffusion region of a second conductivity type in a surface portion of said substrate; a plurality of first conductive layers of the second conductivity type provided for the memory cells respectively each having a portion in contact with said diffusion region of the corresponding memory cell; and a plurality of second conductive layers provided for the first conductive layers, each having multiple contacting portions, each contacting portion contacting a respective first conductive layer, each contacting portion being laterally removed from the memory cell contacting the corresponding first conductive layer.

Claim 12

The semiconductor memory device according to claim 7, wherein a first insulating film is on said array of memory cells, and each first conductive layer is connected to a corresponding diffusion region via a first contact hole in said first insulating film.

Claim 13

The semiconductor memory device according to claim 7, wherein a second insulating film is on said first insulating film and said plurality of first conductive layers, said plurality of second conductive layers are on said second insulating film, and each second conductive layer is connected to a first conductive layer via a second contact hole formed in said insulating film.

Claim 14

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; an array of memory cells, each cell having a diffusion region of a second conductivity type in a surface portion of said substrate; a plurality of first conductive layers of a second conductivity type provided for the memory cells, each having a portion in contact with the diffusion regions of at least two adjacent memory cells; and a plurality of second conductive layers provided for the first conductive layers, each having a portion contacting a first conductive layer and located between the two adjacent memory cells.

Claim 15

A semiconductor memory device comprising: a semiconductor substrate of a first conductivity type; an array of memory cells, each cell having a diffusion region of a second conductivity type in a surface portion of said substrate; a plurality of first conductive layers of a second conductivity type provided for the memory cells, each having a portion in contact with the diffusion regions of at least two adjacent memory cells; and a plurality of second conductive layers provided for the first conductive layers, each having a portion contacting a first conductive layer and located between the two adjacent memory cells.

Claim 16

A semiconductor device comprising a first row of memory cells; a second row of memory cells substantially parallel to the first row; a first lower conductive layer having a contact area with a diffusion region in a cell in the first row; second lower conductive layer having a contact area with a diffusion region in a cell in the second row; a first upper conductive layer having a lateral dimension substantially parallel to the first row, and having a contact area with the first lower conductive layer displaced from the contact area between the first lower conductive layer and the diffusion region in the cell of the first row in a direction along the lateral dimension; and a second upper conductive layer having a lateral dimension substantially parallel to the second row, and having a contact area with the second lower conductive layer displaced from the contact area between the second lower conductive layer and the diffusion region in the cell of the second row in an opposite direction along the lateral dimension.

Claim 17

A semiconductor device comprising a first row of memory cells; a second row of memory cells substantially parallel to the first row; a first lower conductive layer having a contact area with a diffusion region in a cell in the first row; second lower conductive layer having a contact area with a diffusion region in a cell in the second row; a first upper conductive layer having a lateral dimension substantially parallel to the first row, and having a contact area with the first lower conductive layer displaced from the contact area between the first lower conductive layer and the diffusion region in the cell of the first row in a direction along the lateral dimension; and a second upper conductive layer having a lateral dimension substantially parallel to the second row, and having a contact area with the second lower conductive layer displaced from the contact area between the second lower conductive layer and the diffusion region in the cell of the second row in an opposite direction along the lateral dimension.

Claim 18

The semiconductor device of claim 11, wherein the first upper conductive layer includes a first width dimension in a portion opposite the contact area with the first lower conductive layer; and a second width dimension, the first width dimension being larger than the second width dimension, and the second upper conductive layer includes a first width dimension in a portion opposite the contact area with the second lower conductive layer; and a second width dimension, the first width dimension being larger than the second width dimension.

Claim 19

The semiconductor device of claim 12, wherein the first upper conductive layer includes a third width dimension in a portion opposite the first width dimension in the second upper conductive layer, the third width dimension being smaller than the second width dimension in the first upper conductive layer, and the second upper conductive layer includes a third width dimension in a portion opposite the first width dimension in the first upper conductive layer, the third width dimension being smaller than the second width dimension in the second upper conductive layer.

Claim 20

The semiconductor device of claim 13 further including a third row of memory cells substantially parallel to the second row; a third lower conductive layer having a contact area with a diffusion region in a cell in the third row; and a third upper conductive layer having a lateral dimension substantially parallel to the third row, and having a contact area with the third lower conductive layer displaced from the contact area between the third lower conductive layer and the diffusion region in the cell of the third row in the direction along the lateral dimension.