Planar-type microwave integrated circuit with at least one mesa component, method of fabrication thereof

Claim 1

A method for the fabrication of a planar-type microwave circuit having at least one mesa type component, said method comprising the following steps: a) shielding of a planar surface of a semiconductor substrate with a barrier layer made of dielectric, masking and etching of the barrier layer to bare a first region wherein a mesa component and a recess that surrounds it are to be formed; b) hollowing, by etching, of the first region up to a depth equal to the height of the mesa component to form a groove; c) epitaxial deposition of layers of semiconducting materials to a thickness equal to the depth of the groove; d) deposition of a second barrier layer, made of a dielectric, masking and etching of this barrier layer to mask the region wherein the mesa component is to be formed but to bare the region wherein the recess that surrounds it is to be formed; e) etching of the epitaxial layers deposited in the groove except those that are masked, until the semiconducting substrate is reached; f) passivation of the flanks of the mesa by a passivation layer and deposition of a dielectric having the same heat expansion coefficient and the same dielectric constant as the substrate to fill the portions of the groove remaining; g) planarizing of the dielectric which fills the groove, masking and depositing electrical contacts on the planar and mesa components, and the making of interconnections therebetween on the planarized dielectric which fills the groove in microstrip lines; h) thinning of the substrate from its rear face in order to adjust the impedance of the microstrip lines; i) perforation of contact re-making features through the rear face of the substrate and j) deposition, on the rear face of the substrate, of a ground plane metallization.

Claim 2

A method for the fabrication of a planar-type microwave circuit having at least one mesa type component, said method comprising the following steps: a) shielding of a planar surface of a semiconductor substrate with a barrier layer made of dielectric, masking and etching of the barrier layer to bare a first region wherein a mesa component and a recess that surrounds it are to be formed; b) hollowing, by etching, of the first region up to a depth equal to the height of the mesa component to form a groove; c) epitaxial deposition of layers of semiconducting materials to a thickness equal to the depth of the groove; d) deposition of a second barrier layer, made of a dielectric, masking and etching of this barrier layer to mask the region wherein the mesa component is to be formed but to bare the region wherein the recess that surrounds it is to be formed; e) etching of the epitaxial layers deposited in the groove except those that are masked, until the semiconducting substrate is reached; f) passivation of the flanks of the mesa by a passivation layer and deposition of a dielectric having the same heat expansion coefficient and the same dielectric constant as the substrate to fill the portions of the groove remaining; g) planarizing of the dielectric which fills the groove, masking and depositing electrical contacts on the planar and mesa components, and the making of interconnections therebetween on the planarized dielectric which fills the groove in microstrip lines; h) thinning of the substrate from its rear face in order to adjust the impedance of the microstrip lines; i) perforation of contact re-making features through the rear face of the substrate and j) deposition, on the rear face of the substrate, of a ground plane metallization.