Process for fabricating monolithic microwave diodes

Claim 2

A process for fabricating monolithic microwave devices, comprising the steps in following sequence: i. providing a semiconductor substrate; ii. epitaxially growing a semiconductor layer structure including an etch stop layer having a first side on said substrate; iii. forming a metallic heat sink on the opposite side of said semiconductor layer structure; iv. removing, using said etch step layer, said semiconductor substrate from said first side of said semiconductor layer; v. etching the first side of said layer structure to defined therefrom separate active element portions all mounted on said metallic heat sink; vi. coating a dielectric onto said active element portions; vii. forming vias, bond pads, and metallization so that said metallization connects said active element portions to said bond pads.

Claim 3

A process for fabricating monolithic microwave devices, comprising the steps in the following sequence: i. providing a semiconductor substrate; ii. forming a semiconductor diode layer structure having a first side on said substrate; iii. forming a metallic heat sink on the opposite side of diode layer structure; iv. removing said semiconductor substrate; v. etching said diode layer structure on said first side to separate it into separate diode portion all mounted on said metallic heat sink; vi. coating a first layer of dielectric onto said diode portions; vii. forming a first metallization on said first dielectric layer, and configure a predetermined first network of passive elements or connections; viii. coating a second layer of dielectric onto said first metallization and first dielectric layer; and ix. forming a second metallization on said second dielectric layer and configure a predetermined second network of passive elements or connections in electrical communication with said active device areas.

Claim 4

A process for fabricating monolithic microwave devices, comprising the steps in the following sequence: i. providing a semiconductor substrate; ii. forming a semiconductor diode layer structure having a first side on said substrate; iii. forming a metallic heat sink on the opposite side of diode layer structure; iv. removing said semiconductor substrate; v. etching said diode layer structure on said first side to separate it into separate diode portion all mounted on said metallic heat sink; vi. coating a first layer of dielectric onto said diode portions; vii. forming a first metallization on said first dielectric layer, and configure a predetermined first network of passive elements or connections; viii. coating a second layer of dielectric onto said first metallization and first dielectric layer; and ix. forming a second metallization on said second dielectric layer and configure a predetermined second network of passive elements or connections in electrical communication with said active device areas.

Claim 5

The process of claim 2, wherein said network of passive elements comprises capacitators formed on said first dielectric layer and other elements formed on said second dielectric layer.

Claim 6

The process of claim 1, wherein said dielectric comprises polyimide.

Claim 7

The process of claim 4, wherein titanium is deposited on said semiconductor layer structure before said dielectric is coated on.

Claim 8

The process of claim 4, wherein said a layer of metal is evaporated onto said semiconductor layer structure just before said dielectric is coated on.

Claim 9

The process of claim 1, wherein said step of etching said semiconductor layer structure comprises depositing a patterned metal layer over said layer structure to serve as a hardmask.

Claim 10

The process of claim 7, wherein said step of etching said semiconductor layer structure comprises depositing a patterned metal layer over said layer structure to serve as a hardmask, and wherein said etching step undercuts said semiconductor layer structure beneath said hardmask.

Claim 11

The process of claim 7, wherein said step of etching said semiconductor layer structure comprises depositing a patterned metal layer over said layer structure to serve as a hardmask, and wherein said metal hardmask is left in place after said etching step to assist in formation of electrical contact to said semiconductor layer structures.

Claim 12

The process of claim 2, wherein said first dielectric layer is thinner than two microns thick and said second dielectric layer is more than three microns thick.

Claim 13

The process of claim 2, wherein said first dielectric layer is deposited from the vapor phase.

Claim 14

The process of claim 2, wherein said first dielectric layer is deposited from the vapor phase by plasma-enhanced chemical vapor deposition.

Claim 15

The process of claim 2, wherein said first dielectric layer is deposited from the vapor phase and said second dielectric layer is spun on.

Claim 16

The process of claim 2, wherein said first dielectric layer is deposited from the vapor phase by optically-enhanced chemical vapor deposition.

Claim 17

The process of claim 2, wherein at least one of said dielectric layers comprises fluorocarbon polymers and is plasma deposited.

Claim 18

The process of claim 1, further comprising the subsequent step of cutting the finished structure into individual device portions.